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The peak current vs. layout

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chang830

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Hi,
I am designing a block which has an inverters chain as buffer to drive a ~10pF capacitor load. In simulation, I found the peak current is high to ~140mA when the buffer is charging the load capacitor. Then when I layout the output buffer, what width I should select for VDD/GND line. It should be wide enough to tolerate the high to 140mA current? After all, it is instanious current. If so, it will consume too much die area.


What should I do?

Thanks
 

Choose the width accroding to average current.
 

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    chang830

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You will need to deside firstly which metal to use. The higner the metal layer the less resistance,ie metal one has the highest metal resistance . To do this you need to find out the sheet resistance of the metal and calculate from there. If it is too thin you risk electromigratoi n and ohmic voltages drop..

Resistance - R= (p/ t) * (L/W) = Rs * (L/W) where Rs is the sheet resistance in ohms per sq .

as an old rule of thumb it used to be 1um per mA .
 

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    chang830

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flushrat said:
Choose the width accroding to average current.
Click to expand...

I have a little addition to the above.

The average current depends on the input excitation and the level of switching taking place at that moment or for the time period. Thus it is better to choose a input excitation which will cause a maximum switching activity for that block. This is particularly importatnt if after a logic block the inverter appers and for one set of input excitation the switching acitivity may be near zero and for others , say, it switches in every clock edge or so. Thus thinking of this is also important, as far I can understand.

sankudey
 

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    chang830

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we take the average current or peak current/5 , whichever is more.
For EM related issues its better if the width of the metal/current follows the ratio 1micron/1mA .
Saying this, u can take advantage of taking the net in different metals one over the other. ( say M1 and M3 ) in this way it wont consume much of ur area and alos satisfies the EM criteria.
 

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    chang830

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you can reference foundry's edr rule, in that you can see the DC current density and rms current density of metal, in your case you can take the rms current density for reference.
 

In the process document you will find the dc current for each metal layer. The transient current value equals to the dc value multiplied by 10
 

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