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SDF file, Why there exist the negative time check

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tukken

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$recrem(posedge cdn,

Why there are an negative timing check.
such as
(RECREM (posedge CDN) (posedge CK) (0.115559::0.115559) (-0.103630::-0.103630))

Why there exist negative timing check,
Pls help me
 

english there exist negative

Does any body could help me, thanks.
 

negitive timings in sdf

Neagtive timing check is applied when the Flip Flop or RAM etc whose timing is being constrained contains some logic in addition to the actual synchronous element. By synchronous element I mean the logic that is triggered by clock. An example would be a scan enabled flip flop. This would have a MUX added before the actual FF. If the data is delayed significantly when passing through the MUX we could get a negative hold time and enhanced setup time. The other example could be a RAM/microcontroller library cell with its own clock tree. The clock being input is delayed inside the library element and this could result in negative setup time etc.
 
ok, I see, thanks very much, and where could I get more inoformation.
 

Are you using an HDL simulator (Verilog or VHDL)? If so then the user guide and reference manuals of the simulator are good starting points.
 

Verilog, I will check it, thanks.
 

Hi,

You can see negative timing check in the .lib. You can sometime see negative delay.

Regards,
Eng Han
 

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