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DRC check in semi-custom design

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siva_7517

siva_7517

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Hi,

Currently, i am working on 0.18um technology semi-custom from ARM standard cell. After finish layout design in Encounter, i try to stream in into Virtuoso cadence to do drc checking.
Unfortunately when i stream in to Virtuoso from Encounter to do a drc check, I cant see the the transistor level of my design. It is in a abstract view, that means i only can see the standard cell in virtuoso environment. How can i see the transistor level of my design?

Thanks in advance.
 

Encouner uses abstracts of the layout and lef files.
What you need to do is to def in and then change the abstract view to layout view.
you can do this quickly by doing a search for all instances and add a critera to search for abstract then tell it to replace all to the layout view.
or
select the instance, click on proberties and change the View to layout

Added after 2 minutes:

I meant to say make sure once you have defed in ( streamed in) make sure you SAVE it or you'll lose it all in a crash !! its happened to me many a time :(
 

    siva_7517

    siva_7517

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