How to automatize a testbench environment?

Hi
I want to automized my testbench enviornment.
Right now i am doing manually . Can anyone suggest me how to automized my
testbench enviornment.

Re: Testbench Automation

well, what do u mean by automize...isn't the testbench already a program u write and it does all the checking...elaborate more please to be able to help u???

Re: Testbench Automation

Hi
I am doing it manually means suppose i have to run a particulae test case for that i am running that particular test case and cheking it manually on the waveform .

Regards

Added after 10 seconds:


Hi
I am doing it manually means suppose i have to run a particulae test case for that i am running that particular test case and cheking it manually on the waveform .

Regards

Testbench Automation

i think what u r looking out for is, how to do regression, right ?

Re: Testbench Automation

No I am not looking for regression.
ok i will clarify myself.
when we are checking for data integrity and packet is small in size then
by looking on the waveform we get to know,but if packet size is big say 3000-
4000 bytes of data is there then checking on waveform is prone to errors.
That is why i wanted to ask if instead looking on the waveform is there any other
way is there or not.

Regards

Testbench Automation

u can use assertions in u r code and it would display the messages.

Regards,
dcreddy1980

Testbench Automation


that will help

Re: Testbench Automation

s_vlsi said:

No I am not looking for regression.
ok i will clarify myself.
when we are checking for data integrity and packet is small in size then
by looking on the waveform we get to know,but if packet size is big say 3000-
4000 bytes of data is there then checking on waveform is prone to errors.
That is why i wanted to ask if instead looking on the waveform is there any other
way is there or not.

Regards

Click to expand...

What you need to develop is called a "scoreboard" in Verification. It essentially does the following: (Here SV refers to SystemVerilog)

1. Keeps track of incoming packets (Use SV Queue to store it)
2. Whenever an output packet appears, it pops an elemtn from the packet queue
3. Passes it through a reference algorithm (that you should have modeled using higher level constructs such as in SystemVerilog) and makes an "expected packet"
4. Compares the expected and the actual and declares pass/fail

This is an involved job and requires a while to get it right, but the benefits are far encouraging than the time spent.

ALso as some one else mentioned, assertions are a good choice too. If it is a simple, not deeply pipelined design, then a simple assertion such as:


Will do the job for you. Above code is using SystemVerilog Assertion, not compiled for correctness - just to give you an idea.

BTW, there is more automation that you can do in generator side, you may want to look at VMM kind of methodology. We just finished writing a book on adopting VMM in real life designs. See details in signature below.

Good Luck
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/[/list]

Testbench Automation

Scoreboarding is the one generally followed.

Testbench Automation

Try to use the assertions and function coverage measure in your verification env.

Testbench Automation

In the name of God

A simple solution is to export results to a txt file (using for eg. Modelsim) and verify results by a C program witch written by you. Scoreboard is the regular method for solving this problem.
Regards