What does it mean that external ports should be connected through IO in ASIC design?

Hi
I have doubt.In my asic design,I was instructed that some external ports should be connected thru io.v.What is the exact meaning of this.I am begiiner in asic design.I was told in my company that it will connected to IO of the cell.What does it mean.Thanking you
VSRPKUMAR

Re: Hi

Hey Kumar,
When you think of a asic chip , there are 2 parts to be considered
* Core
* I/O pads
Core consists of the logic to perform what ever your chip's functionality . Genrally works on a lower voltage ( typically 3.3 V or 1.2 V) to save power.
I/O pads are used to connect the core to the external pins. The reason that this needs to be there can be appreciated if you just think of the load that these need to drive. These cells typicallly run on highet voltage . Let me know if you need more info

Re: Hi

Give me some more explanation.If u have any document,please upload.Thanking you

Re: Hi

ya more explanation or any document explanining would be appreciated from begineers like us.

i would add up to the Q, that when we import a design in SOC Encounter, we get 3 things

Top Module
Core
Hard Macros

first of all what r these, do we get lthese 3 things whatever may be the verilog synth file?????

thanks in advance,
Prasad

Re: Hi

Unfortunately I donot at present have any document that I can share with you guys but let me try putting more info into this.
When you consider any design that needs to be fitted to a asic . You will have
Top module -> This is would be the RTL logic that you synthesised.
I/O pads -> Required because the pin out of the chips have huge capacitance and the small transistors in your logic gates will not be able to drive such huge loads . So what is generally used is a cascade of buffers to drive this ( buffers with increasing sizes connected serially) which would drive the external world pins.
Hard macros -> There will be parts of designs which you will not be synthesising ( for example - memory block , analog/ RF block, vendor IP etc) you will not have any RTL for these but hardmarcos are provided for you directly .

You will be able to get more info on these using any of the ASIC fundamental books.

Re: Hi

semiconductorman can i get your email address, if possible.


one of the questions i have for SOC Encounter is that , do everytime, we have to place those Hard macros in that core, is that the aim of our design?

and how to decide which hard macro would be placed at top, bottom location???


then what about soft macros?

waiting for ur email address also.

Thanking you,
Prasad Shinde

Re: Hi

Please post the reply,
So that i can also kow.Thanking you
VSRPKUMAR

Re: Hi

Hmm ... I'll try making this as short as possible. You code RTL , verify that it's functionally correct make sure your able to do synthesis without any warnings / errors => vola ... you have your soft macro ready . Unfortunately this is no where near the final silicon ... afterall all you do have is a piece of RTL. You got to turn this into silicon which involves mapping your design into a library routing your design ( routing -> process where all your connections b/w standard cells are done) , power routing ( routing power vdd and vss to all the cells) , clk routing etc ... Then you can plan on sending your desing to foundary for getting your silicon .. the final product ! .

Now there will be some parts of the design that you don't design but buy from some one else .. now this guy will say he will not want to share his RTL design ( else you can simply copy of the whole design ) so he gives you a hardmacro that is .. .. for example if you buy say a USB I/P from some external vendor .. he'll tell you that he has a design on this library that takes so x amount of area , has y number of pins . you can go ahead and take the whole design as hard macro. The rest of the design is yours so you have the liberty to place the std. cells that form your design anywhere you want provided they satisfy the setup and hold equations (slacks). But since you don't understand the slacks of the hardmacro you are forced to keep the whole design without distrubing the placement. Your core will be made up of the logic you have created and also the hardmacros that you give you the final product.

Where to place your hardmacros is a dicission taken durning the floor-plan stage of your design.

You have to understand that in order for the final product to work the hardmacro and your design should interface properly that is the intent of any back end designer .

#################################################################
You can send me a personal mail by clicking on semiconductorman that appears on left hand side (just above the jpg image) of this post . I'll reply to you and so will many other knowledgable members of this group sending personal mails will defeat the purpose of this forum.

Hi

Thats a wonderful explanation. Thanks Semiconductor man.