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how to delay a 10Gbps signal in CMOS

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beabroad

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i want to design a CMOS subcircuit to delay 10Gbps signal, and find the inverter can not work for they introduce too much capacitance.

i am considering transmission line. any idea? thanks.
 

try single stage - cascaded - distributed amplifier (SSCDA).

this might provide the delay you need. it is basicely cascaded inverters but using inductive peaking technique to increase the bandwidth.

there are a lot of papers on this topic in IEEE.

Hope this will help!
 

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    beabroad

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is distributed amplifier too large for the circuit? it needs inductors. or maybe i can use transmission line to replace the indutor
 

beabroad said:
is distributed amplifier too large for the circuit? it needs inductors. or maybe i can use transmission line to replace the indutor
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I really dont know, it depends on how much delay you want. and i dont think the transmission line on the chip will provide too much delay by itself.

if you put the transimission line off chip, it is another story.
otherwise, i think using inductor would be more area effcient than transmission line.

and for cascaded single stage DA, just one inductor for one stage. and if you want more delay, put more stages. and the delay is the result of using both inductor and capacitor.
 

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    beabroad

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how about using delay cell of ring oscillators? can it provide enough bandwidth and delay?
 

Hello ,

how about using a buffer,by using this u can get some delay

Regards
Raj
 

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    beabroad

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good point. another problem is which kind of buffer is better?
i used to use series of inverters, but 10G is too fast to use that.
 

RC circuit?
 

how about a microstrip delay line ?
 

Could the following help you....
IEEE,JSSC,NOV-2005,A monolithic Digitally controlled delay elemnt, M Maymandi...
it says in 0.18umCMOS, from 2ps above delay resolution...
 

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