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which kind of amp should I use ?

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hitlgc

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hi all

I want to design a CMOS buffer op amp. The Cl=90pF, input signal is a 30MHz pulse swing from 0v to 1.25v. The close loop gain is 4,Vdd is 12v.

Which structure is the best choice for my design?

thanks&regards
 

1. fin=30MHz, to achieve 1% accuracy of settling , BandWidth=5*fin= β*fu, β=1/4,
so fu=20*fin=600MHz
2. fu = gm/(2*pi*CL) ==> gm=2*pi*fu*CL =339mA/V
3. cause CL is too large, 2-stage OPamp is not feasible, simple Gm amplifier maybe the best choice , folded-cascode will consume too much area.
 

    H

    hitlgc

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dear btrend,
why and how you have chosen bandwidth=5•fin
 

    H

    hitlgc

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Dera btrend,

Why 2-stage OPamp is not feasible?
Will you please explain it in detail?

thanks a lot!
 

dear hitlgc
for large capacitive load,your frequency response of two stage opamp will be hugely deterioted because your second pole (p2=gm/Cload) will come closer to the dominant pole and hence your frequency compensation will become a tedious job.
while using single stage opamp(folded cascode) we have only one dominant pole.hence increasing the load will not have any effect on the frequency compensation(only your bandwidth will be reduced).
Simple Gm amplifier consumes less area but it will not give the gain which folded cascode can provide.
 

    H

    hitlgc

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avinash said:
dear btrend,
why and how you have chosen bandwidth=5•fin
Click to expand...
consider the step response of a single pole OP, like A(s)=A0/(s/ω0+1), the output of this OP configured as closed loop (buffer with feedback factor β), will be Acl(s)=A(s)/(1+A(s)*β)
==> Acl(s)=[A0/(1+A0*β)]*{1/[1+s/[(1+A0*β)*ω0]}~=Acl0*[1/(1+s/(β*ωu)]
i.e. Vo(s)/Vi(s)=Acl0*[1/(1+s/(β*ωu)]

back to time domain, and assume A0*β >> 1, then Acl0=1/β
u will find Vo(t)=Vi(0)*(1/β)[1-exp(-t/τ)] where τ=1/(β*fu)
and the settling behavior is controlled by the term [1-exp(-t/τ)],
so if 1% accuracy is required, 1-exp(-t/τ)=0.99 ---- (1)
solve (1), u can find
===> t=5τ ----(2)
and this time should be less than 1/fin, ---(3)
(2) ≤ (3) ===> 5τ≤1/fin
==> 5/(β*fu) ≤1/fin
==> fu ≥ 5*fin/β
 

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    hitlgc

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thank you for your explain.

in my opinion, for a two stage op amp,the second stage is used to obtain large output swing.

so if I use a simple Gm amplifier, how could I obtain large output swing?

in my design, the input is a pulse from 0 to 1.25v, so I hope the output swing from 0 to 5v, if the power is 12v, is it possible for single Gm amp or folded cascode amp?

thanks®ards
 

dear Btrend ,
which opamp can provide the UGB of 600MHz as you mentioned.simple folded cascode can provide upto 100-150MHz .
 

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    hitlgc

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which opamp can provide the UGB of 600MHz as you mentioned.simple folded cascode can provide upto 100-150MHz .
Click to expand...
if the loading cap is not so large, it is not so hard to get fu=600MHz. the thing u pay to earn this fu is the large current it consume.
btw, u can relax the spec. to 3τ, which equavilent to 5% setting accuracy. and ur fu will reduce to 360MHz.
I must say that , usually the value of fu from theory is a minimum requirement. but in real application, some gain reduction is allowable. there is always compromise between gain and speed.

so if I use a simple Gm amplifier, how could I obtain large output swing?
Click to expand...
from ur spec. Vout is only 4*1.25=5V, and ur VCC=12V. so the Vout is not so large as compare to VCC. I think GM amp. can fit ur need. usually large output swing is refered to Vout > 0.8Vcc in my knowledge.
 

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    hitlgc

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sorry to cut in.

Betrend, i don't understand why the time constant equals to β*ωu. the feedback simply makes the bandwidth (1+β*A0) times larger. i don't know why in your proof:


Acl(s)=[A0/(1+A0*β)]*{1/[1+s/[(1+A0*β)*ω0]}~=Acl0*[1/(1+s/(β*ωu)]
Click to expand...

in my opinion, it should be:
Acl(s)=[A0/(1+A0*β)]*{1/[1+s/[(1+A0*β)*ω0]}~=Acl0*[1/(1+s/ωu]
where ωu=(1+A0*β)*ω0.

5T<=1/fin => 5/fu<=1/fin => fu = 5*fin

thx for correction
 

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    hitlgc

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in my opinion, it should be:
Acl(s)=[A0/(1+A0*β)]*{1/[1+s/[(1+A0*β)*ω0]}~=Acl0*[1/(1+s/ωu]
where ωu=(1+A0*β)*ω0.
Click to expand...
the ωu is unit gain bandwidth, and it is equal to A0*ω0. and this value is constant, and β is the feedback factor, which happen only in closed loop .
 

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    hitlgc

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thx for your explanation. i thought ωu was the bandwidth.

Added after 1 hours 15 minutes:

can we calculate the biasing current like this:

I = Cload * dV/dt = Cload * swing voltage / (1/fu) = 90E-12 * 1.25 * 600E6 = 70mA

?
thx
 

what u had calculated is the minmum slew rate required at the output. but the output dV is not 1.25, it is 1.25*4=5V, as stated in the first post.
moreover, if u use this current, ur output will always like a triangle wave, not pulse like.
 

Btrend,
to make the output pulse like, what value of bias current we need? do you know some materials about the reference current calculation?
 

1. if u want to get pulse like output, ur OP should have not be slew rate limited
2. u can refer to some text book talking about step response of OP
3. the easy way is that u can design a simple OP , and then do some SWEEP (either to Cload or Ibias ) simulation to find the best value of ur bias current.
 

Dear Btrend,

could you please tell me what kind of OP have slew rate limited, and what kind don't?

thanks
 

1. slew rate limited occured whenever the total bias current charge or discharge Cload with a limit rate, in this situation, ur OP is not an amplifier instead it become to be a pull high or pull low device (i.e. in saturate state). only after the voltage at Cload back to the nominal bias point, ur OP is an amplifier again.
so if ur load is too large , and ur bias current is not large enough to provide rapid charging/discharging current, ur OP will slew rate limited no matter what kind of topology u choose for ur OP.
2. there are many papers discussed this kind of design, and they used different techniques to remove this kind of restriction. such as adaptive biasing, pre-charging,... u can search them with key words , such as "slew rate limit" .
 

wholx said:
I = Cload * dV/dt = Cload * swing voltage / (1/fu) = 90E-12 * 1.25 * 600E6 = 70mA
Click to expand...
SR limits the maximum power bandwidth, fp, defined as the frequency at which a sine wave input, at the rated output voltage, begins to exhibit distortion. So fp>30E6, output Vr=4*1.25=5V, then SR>fp*(2*pi*Vr)=942V/us, I>SR*CL=85mA.
 

Btrend,
still a little question here.



as you said, ωu is the gain bandwidth product, a constant value. so ωu = A0*ω0
where A0 is the open loop gain, ω0 is the open loop bandwidth.

as you calculated:

fu = gm/(2*pi*CL) ==> gm=2*pi*fu*CL =339mA/V
Click to expand...

did you suppose the open loop gain as unity?

since we can calculate the relative error from the β and A0 like this:

1/(β*A0)=relative error
let's say 1% in the application, then A0 = 1/(β*1%)=1/(1%/4)=400

if the open loop bandwidth ω0=gm/(2*pi*CL),
thus we can calculate gm like this:

fu/400 = gm/(2*pi*CL), so gm is 400 times smaller as what you got.

am i right?
 

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