Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

optimizing the dead zone in the PFD/CP

Status
Not open for further replies.
mmohsen

mmohsen

Advanced Member level 4
Joined
May 19, 2005
Messages
100
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,298
Activity points
2,425
i am designing PDF/CP for 2.4GHz PLL (Frequency Synthesizer)
and i am using the conventional PFD design, i have a problem now in optimizing the dead zone to match my specs , i tried to increse the rest time (add delay to the rest bath) as many papers said but i found no significant difference ,

could anyone tell me if there is any design parameter that could vary the dead zone , or any paper or refrence that discuss this issue more deeply.

thanks in advance,.

mmohsen
 

try to put delay in the path of up and down signals
which tool do u use to simulate the dead zone
also what is ur reffernce frequncy ?
khouly
 

I think adding delay in reset path is an effective way to eliminate the dead zone.

So maybe your simulation needs to check again. Or please show how do you simulate the dead zone problems ?

Yibin.
 

i am using spectre ,
my ref frequency is 5MHz
and i am ploting Iav v's phase error

i tried the delays before with the up and dn and it gives results till a certain limilts
but it did not give me my spec

i need to know the limitations on the delay which actually is related to fref
is there any limitations??

thanks for reply
 

mmohen wrote:
i am using spectre ,
my ref frequency is 5MHz
and i am ploting Iav v's phase error

i tried the delays before with the up and dn and it gives results till a certain limilts
but it did not give me my spec

i need to know the limitations on the delay which actually is related to fref
is there any limitations??

thanks for reply
Click to expand...

I think 5MHz is very easy to deal with the dead zone problem.
Let me make sure your simulation is ok or not.
1.fref and fvco is the two input of PFD.
2.let fref and fvco is the same frequnecy and the same phase, in your case that's 5MHz.
3.run .tran about 5 cycle.
4.measure the up and dn pulse width of PFD output.
5.the pulse width of 4 is called idle pulse.
6.if the idle pulse can turn on the charge pump, then you eliminate the dead zone problem.

Is that clear ?

Yibin.
 

hello ,Yibin,
i do not understand :"5.the pulse width of 4 is called idle pulse. "

what is your reasons to measure the 4 pulse width as the idle pulse? why do not choose 1 or 2 pulse width?



thank you !


a greenhand.
 

1.fref and fvco is the two input of PFD.
2.let fref and fvco is the same frequnecy and the same phase, in your case that's 5MHz.
3.run .tran about 5 cycle.
4.measure the up and dn pulse width of PFD output.
5.the pulse width of 4 is called idle pulse.
6.if the idle pulse can turn on the charge pump, then you eliminate the dead zone problem.

Is that clear ?
Click to expand...

i donot understand 5,6
how could i find the dead zone by this way?
do u mean 4 pulses with diffrent pulse widthes?? sweep

all what i had understanded from your reply that you are trying to inspect how much delay you need to eleminate the Dead zone ?? is it true ??

would you please clarify your reply ,,

thanks in advance

mmohsen
 

no he means the pulse width in step 4 and not 4 pulses.now i can make something clear.the dead zone depends on the critical path in the pfd u use.naturally when the phase difference between the input and reference becomes smaller than this delay.then naturally the pfd is not going to output any signal.dead zone cannot be eliminated but only minimized.u can also try using a dynamic logic pfd.

regards
amarnath
 

amarnath wrote:
no he means the pulse width in step 4 and not 4 pulses.now i can make something clear.the dead zone depends on the critical path in the pfd u use.naturally when the phase difference between the input and reference becomes smaller than this delay.then naturally the pfd is not going to output any signal.dead zone cannot be eliminated but only minimized.u can also try using a dynamic logic pfd.
Click to expand...

thanks for reply

first : if u understand the reply of yibinhsieh please clarify it again in more details.

second : i think that this defination of the dead zone problem is not clear as from my point of view this problem comes from : when the pahse error is small the pfd produce small pulse which cannot switch ON the charge pump as this switch has certain i/p capacitance so to eleminate this problem we have to make the rest pulse with min. width that could turn On the CP Switches so when a small phase error occurs it will be added to that pulse so we will be sure that the PFD/CP respondes to the phase error. so i think the problem is related to both PFD and CP together ,
**Waiting your feedback

regards ,..
mmohsen
 

    V

    Points: 2
    Helpful Answer Positive Rating
that is one perspective of the dead zone problem.another perspective is that take a simple example.suppose ui have a circuit (digital).can u make it generate a pulse whose width is less than the delay through the digital circuit.that is what i exactly i mean in case of the pfd also.in case of a pfd designed using nang gates ,it has a very long critical path.so any pulse width smaller than this delay cannot be generated.hope iam clear.

regards
amarnath
 

    mmohsen

    mmohsen

    Points: 2
    Helpful Answer Positive Rating
i think your point is clear now , thanks alot

so there will be within an archetcture a certain dead zone (eg:built in)

what about yibinhsieh method did got it ??


regards,..

mmohsen
 

yibinhsieh method only suggests a method to avoid partial turning on of the charge pump transistors by increasing the width of the pulses after lock has been attained,so that more time is available for the charge pump transistors to source and sink current.so in order to avoid partial turning on of the CP transistors even when ur PFD is responding to an input phase difference, this method is ok.

regards
amarnath
 

Optimizing the deadzone is simply set the ratio between rise/fall time of the charge-pump currents and the minimum pulse time of the phase/frequency detector to a value where the nonlinearity of the composite behaviour of both does not introduce more noise than the other noise sources.

If you model the charge-pump as a switched RC filtered current ramp. And if the minimum pulse time is not considerable higher than the rise/fall times. Then the charge integration over one reference cycle result in a nonlinear function from the phase difference.

If these model applies the mention ratio above should be 2-5. If you compare the model with the spice results of the integration you find will be satisfied.


I also discuss this in
 

amarnath said:
In case of a pfd designed using nand gates ,it has a very long critical path.so any pulse width smaller than this delay cannot be generated.hope iam clear.
Click to expand...

So how can we measure the dead zone of the pfd alone, in order to know whether it is the dominant, or the loading of the CP is the effect which cause the increase of the dead zone ?
 

naturally both with be causing the dead zone .u can eliminate that due to partial turning on/off of the charge pump transistors by increasing the width of the reset pulse.for optimizing the delay through the pfd,u need to use a d flip flop with minimal delay.u can use a d flip flop made using pass transistors or u can also u tspc structure.another pfd which is very good for high speed operation is the dynamic logic pfd.

regards
amarnath
 

eng_Semi,

it is not which one is dominant. It is the non-appropriate relation between minimum pulse time of the detector and the rise/fall time of the pump current.

There is no dead time in the detector! There is no dead time in the pump! If you simulate the charge over time/phase difference the resulting curve is looking like to have a dead zone.
 

rfsystem said:
eng_Semi,

it is not which one is dominant. It is the non-appropriate relation between minimum pulse time of the detector and the rise/fall time of the pump current.

There is no dead time in the detector! There is no dead time in the pump! If you simulate the charge over time/phase difference the resulting curve is looking like to have a dead zone.
Click to expand...


soyou seem to say that the pfd can respond to the finest of phase differences between the reference and the vco output.then such a situation would be great.just answer this question:if u have a digital circuit,the input to whom is a pulse whose pulse width is less than the delay through the circuit,do you think the pulse will reach the output?if u answer this u can conclude whether a pfd has a build in dead zone or not.dead zone means nothing but a period of time where ur pfd does no respond to the inpt at all. and the pll in this case behaves as an open loop system.

regards
amarnath
 

The minimum input pulse time to the PFD is not equal to the minimum pulse time of the UP or DOWN outputs of the PFD. The PFD operate only on one rising or falling edge of the inputs. It is edge triggered. The linearity performance will be impacted by the opposite edge if the pulse time is equal to the actual time/phase difference. If the PFD is built with two register which are clocked by the two inputs and are asynchron reset by the AND of the UP and DOWN there is no dead time effect in the PFD.
 

rfsystem wrote:
The PFD operate only on one rising or falling edge of the inputs. It is edge triggered. The linearity performance will be impacted by the opposite edge if the pulse time is equal to the actual time/phase difference
Click to expand...

i completely agree with you but i am some what confused i found in the paper discussing the PFD's types that there are types having DZ and others have no(small) DZ and they relate thier behavior to their turn on time i think as amarnath said in his defination ????

**Did you have any link or paper that discuss this issue in more details??

regards,..
 

yes there are many papers which speak on this.there is no doubt that there is going to be an associated dead zone for a pfd,since it has a feedback path(conventional pfd).

Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang and Wei-Bin Yang:” A Difference detector for Low Jitter PLL.”, Electronics Circuits and Systems, 2001.ICECS 2001.The 8th IEEE International Conference on, Volume: 1, 2001, pp 43-46 vol.1.

regards
amarnath

Added after 1 hours 51 minutes:

u can try to minimize the dead zone due to the pfd by increasing the width of the reset pulse,by doing this u are allowing this pulse to propagate to the output instead of it being eliminated by the pfd itself.but this increase in reset pulse width is not without its disadvantages.it can lead to frequency jitter when charge pump currents are not matched.also it will lead to a greater ripple at the output,which will lead to spurs,so there is a trade off.

regards
amarnath
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top