vibeguy
Newbie
So I have two questions, and these are kinda hefty so I apologize for that
Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement that in an FPGA with the same layout?
My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close.
Q2: If we design a circuit implementation inside an FPGA, and only use a certain fraction of available blocks, how weakly are the unused blocks connected with the rest of the circuitry? For example, if power analysis is performed on the FPGA, how much will the unused parts of the chip affect the results?
Love to hear some thoughts!
Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement that in an FPGA with the same layout?
My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close.
Q2: If we design a circuit implementation inside an FPGA, and only use a certain fraction of available blocks, how weakly are the unused blocks connected with the rest of the circuitry? For example, if power analysis is performed on the FPGA, how much will the unused parts of the chip affect the results?
Love to hear some thoughts!