Issues with code for generic mux with FOR

Hello,
I'd like to build de multiplexer whose number of inputs could be fixed with parameters or defines. I'm wondering if those 2 pieces of verilog code produces the same results in my FPGA:
with:
1.
and
2.
Are 1. and 2. equivalent ?
Moreover, 2. fails to synthesize with Quartus

Error: Verilog HDL syntax error at emtrion16550.v(55) near text "for"; expecting an identifier ("for" is a reserved keyword ), or "endmodule", or a parallel statement

Click to expand...

Does anyone know why ?

regards,
Fran6

vhdl generic mux

First of all, code 1 is not a MUX, but rather a multi-input OR gate.

A MUX will have a number of input and an output, plus a selector (which select which of the input goes to the output). An example is a 4-to-1 mux, which have 4 inputs, 1 output, and 2 select lines (which can take the value of 00, 01, 10 or 11 and select which input goes to the output).

The 2nd piece of code will not synthesize because a for loop is not synthesizable. As I written in another thread:

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There is a mistake that many people do when begining to program for FPGA, especially if those people previously programmed structured language like 'C'.

You have to think, throughout your design, that you're implementing hardware functions, and not a sequential program. You have to keep in mind that everything happen in parallel. For example, you can not synthesize a for loop. A for loop is a sequential thing. This is good for simulating (testbenching) only. So, to design something that work like a for loop, you have to synthesize a counter, and do different things depending on the output. The counter become one entity, and the actions (logic blocks) depending on the counter output is another entity.

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Here, if you wish to design a multi-input OR gate, with width parameterizable, a way to do it would be

`define NB_WB_DEVICES 3
wire wb_ack_i;
wire [`NB_WB_DEVICES-1:0] wb_ack_i_mux;

assign wb_ack_i = |wb_ack_i_mux[`NB_WB_DEVICES-1:0];

Note the pipe character ('|', OR) before the wb_ack_i_mux in the above line.

The unary pipe character '|' defined before an identifier is a bit-to-bit OR, meaning that it will take all bits in wb_ack_i_mux[`NB_WB_DEVICES-1:0] and OR it togetter, giving a 1-bit result.

vhdl mux generic

I have my disagreement with FOR loop not being synthesisable . I thing the second one is giving a problem because of the assign statement with FOR .... For statement in verilog can be used only inside a inital / always ... and assign cannot be used inside inital / always . assign is continous assignment !
Second piece of code will give error even on simulation . Please rewrite your code ... You can make your code work but some rework is requried . ..

verilog generate mux

hello,
thanks for your answers.
This solutions:
is exactly what I needed for my multi input OR gate with parameterized number of inputs

I also need to write a mux with parameterized number of inputs. Most of mux that I have seen work with a binary coded signal selector and I don't really see how to deal with this for my problem. I'm thinking about this solution where the signal selector isn't binary coded but is one enable signal per input:
I think this doesn't works because wb_dat_i is an array of address buses of 8 bits and wb_dat_i_enable is just an array of bits. I don't really know how to formulate it.

For the "for" statement, Big Boy say that it is not synthesizable and semiconductorman say it is !! Then who is wrong ? Can it depend of the synthesis tool ?

Fran6

vhdl generic multiplexer

For loop does synthesize.
but as semiconductorman told.. yes it has to be inside a process or an always statement in verilog.
Coz i have used a for loop to design an FIR filter and yes it works very fine ........

parameterized mux

I know it synthesize within a 'generate' block (Verilog 2001). For within procedural block, it may depend on synthesizer.

vhdl parameterized mux

Big Boy said:

I know it synthesize within a 'generate' block (Verilog 2001). For within procedural block, it may depend on synthesizer.

Click to expand...

generate block ... are you sure u are not confusing verilog with vhdl ? I am not sure of verilog 2001 since i have not used this ... But In genral any FOR loop is usally synthasisable unless u do some sought of behavioral code or use disable .. that has been my experience

Added after 9 minutes:

Fran6,
Two things first ... IT is necessary that the select bit be binary else it defeats the whole purpose if each input has one select line ... now it is no more a mux secondly imagine in h/w ....what happens if more than one select line is one at the same time .... and also you cannot have a condition where ur output has multiple drivers!!!!
To code a variable input length please use procedural code instead of continous ... it is much simpler and elgant

vhdl generic

Verilog 2001 add a lot of new features. I'm too are still begining in HDL language, and found that Verilog seemed to have a lot of limitations in regards to VHDL, but with Verilog 2001, Verilog is a lot more mature, closing a great deal of the gap that it was missing from VHDL.

Look at https://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf this a a very good summary of what's new in Verilog 2001.