1 second Analog pulse detection circuit

Hi,
I want to design a pulse detector circuit. If the pulse width equal or more than 1 second, the output must be high. If pulse width less than 1 second, the output must be low.
Is there any way to design it accurately?
Regards.

This is easy with even the simplest MCU or it can be done with a monostable or timer.
If using the monostable or timer, trigger it with the pulse, set it's time-out period to one second and gate the output with the pulse you are detecting. Only pulses longer than one second are allowed through the output gate.

You need to decide two things:
1. how accurate the time window has to be,
2. what do you do after detecting the pulse length - how long does your output have to be valid and what resets it again.

Brian.

Hi,

Could an integrator op amp into a comparator work for you?

Hi,

sounds simple but some informations are missing.

When you say "pulse" ... do you mean HIGH?

Then clear is so far: when the input puLse is HIGH for more than one second, the output should go HIGH.
But how long/short is the input LOW pulse?
And when should the output go LOW?

Please draw a timing diagramm for various situations. Hamd drawn is O.K.

Klaus

Reciprocal counter technique for long pulses most effective way.


AN52-1 Fundamentals of Time and Frequency

http://www.keysight.com/main/facet.jspx?&cc=US&lc=eng&k=an52-1&sm=g

http://www.keysight.com/main/gated....ntContType=sr&fileType=VIEWABLE&searchType=GR

AN200-3 Fundamentals of Time Interval Measurement

http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CCAQFjAA&url=http://www.leapsecond.com/pdf/an200-3.pdf&ei=sp6pVOqHL8yfgwSlxIHwBw&usg=AFQjCNERngBpwCsPHkaobtnn_gVsr9XOeQ&bvm=bv.82001339,d.eXY

AN200-4 Understanding Frequency Counter Specifications

http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CCwQFjAA&url=http://www.leapsecond.com/pdf/an200-4.pdf&ei=C5-pVPirNsKVNv-AhKgB&usg=AFQjCNHmildQb5hs3se65lD1nrycOqhjDw&bvm=bv.82001339,d.eXY

AN-1289 Science of Timekeeping



Background material attached.

KlausST said:

Hi,

sounds simple but some informations are missing.

When you say "pulse" ... do you mean HIGH?

Then clear is so far: when the input puLse is HIGH for more than one second, the output should go HIGH.
But how long/short is the input LOW pulse?
And when should the output go LOW?

Please draw a timing diagramm for various situations. Hamd drawn is O.K.

Klaus

Click to expand...

Hi,
Yes, I mean High with Pulse, 3.3V or 5V.
Low signal time is unknown, I just want the output of circuit insensitive to input less than 1 second HIGH.
Once output is high, it dont have to go low again. The output may be pulse, I can use a latch comparator etc for latch the output.
I attached the example input/output waveform.
Thank you.

Hi,

ats2 said:

it dont have to go low again.

Click to expand...

Never? Really?
Not after the line is LOW for a year?
Not after a new pulse with 0.5s HIGH?
Not after new power up?

Klaus

KlausST said:

Hi,

Never? Really?
Not after the line is LOW for a year?
Not after a new pulse with 0.5s HIGH?
Not after new power up?

Klaus

Click to expand...

Of course after new power up it must be low again. Like I said before, I need latch output, but once output detects 1 sec input, I can use a latch comparator for latching. So it will be insensitive for any input.

How much latency can you tolerate from time pulse reaches 1 sec before
your indication output occurs ?


Regards, Dana.

A solution is to use a reciprocal frequency counter approach, discussed in ref
material I posted for you earlier. Here is a single chip approach to that.
Done in Cypress PSOC, although you can do this in just about any chip. Except
if you need additional analog signal capability that PSOC has. Right hand window
shows resources used/left, most still available for other stuff like display drive,
COM.

This approach has a small latency due to isr needed to generate the indication
a 1 sec pulse was detected. You can eliminate the isr and just use the compare
out of the counter. Or do a full parallel HW approach, chip would support that as
well. There latency would be a few gate delays, << 50 ns I would think.




What is accuracy of measurement you need and max latency to detection ?



Regards, Dana.

I forgot not gate to auto reset the counter when input goes low.



Regards, Dana.