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i assume you mean keepout regions for a PWB
i also assume inner keepout means keeping trace out of the "inside" part of an IC.
if this is the case, the inner keepout may mean that traces from a pin
on one side of the IC cannot go straight through to the other side
for example, this could be an issue for traces used with an op-amp follower
where the inverting input and the output are connected
please provide contest, as ThisIsNotSam and reza147 have asked
the more pertinent information you provide, the better the answer
I have read it in ICC pdf, for providing keepout margin on std cells to reduce the congestion we acn give outer keepout margin and inner keepout margin. Outer i can relate how it will work but i am not able to relate inner keepout margin. for outer tool will not place any cell for the distance we have mentioned. but what about inner? how tool will behave?
As you know, we add outer keepout margin on std cells to prevent other cells placing next to it or reduce congestion. We also add outer keepout margin for sub-blocks.
One example, inner keepout margin requently use for sub-block, in hierarchical design. In this case, you dont wanna place std cells or anything near the boundary of sub-block, you add inner keepout margin. These cells placed near the boundary will cause issue (DRC or other) when merging into its top-block. So, to prevent this issue, we add inner keepout margin in sub-block.
As you know, we add outer keepout margin on std cells to prevent other cells placing next to it or reduce congestion. We also add outer keepout margin for sub-blocks.
One example, inner keepout margin requently use for sub-block, in hierarchical design. In this case, you dont wanna place std cells or anything near the boundary of sub-block, you add inner keepout margin. These cells placed near the boundary will cause issue (DRC or other) when merging into its top-block. So, to prevent this issue, we add inner keepout margin in sub-block.
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