physical synthesis flow

pdef vs def + edaboard

i am just beginning physical synthesis with synopsys' tools, and now i have some problem with the design flow.

Someone told me that the physical compiler can synthesize the RTL code to netlist, but I only know the flow should be logical synthesis -> floorplan -> physical synthesis -> P&R.

If the physical compiler can do RTL to GDSII, that means the input data to psyn are RTL code and the floorplan information in PDEF format, then the question is how can I get the PDEF file without do a pre-synthesis and the floorplan the design ?
or what I have been told is totally wrong ?

So, i wanna know the flow of physical synthesis in detail.
THX

PhysicalCompiler does incorporate a synthesis engine, which can turn RTL codes directly into netlists. Some guys do use this feature, and they believe PC could provide better synthesis results because PC uses a more precise wire load model. So, as far as I know, if you want to synthesis a small module, PC could do you no harm, and if you want to synthesis whole chip, PC is an idea choice, of course, you should provide pdef in this case. you can get pdef from jupiter.

But without a pre-synthesis using DC or something else, how can i floorplan the design, such as defining the core area.

well dude i dunt understand ur question.. but i shall give u the design flow that i know..

MAGMA is the tools which helps in complete RTL to GDSII format design flow (MAGMA doesnt have a simulator)

Setp 1 - Design entry (HDL decide on ur language VHDL or Verilog HDL)

Step 2 - Simulation/ Synthesis - Obtain the netlist ..

Step 3 - System Partitioning -- (ASIC only)


Steps 1,2,3 is refered to as Pre layout simulation

Step 4 - Floor planning -- Floor planning involves various steps such as power padding, macro cell deciding ( soft macro, firm macro and hard macro) deciding the floor planning scheme (Flat or heirachial). Power distibution scheme (power ring,power strap or power mesh)

You have CTS -- Clock tree synthesis --> very important

Step 5 - placement - this decides the percentage of the chip being used and the percentage of chip resources which is free..

Step 6 - Routing -- interconnection between the various components which are placed in the different floors.
wirin can be done using aluminium (.18 micron tech) , copper (0.13 micron tech) or GaAs for (.09micron/90 nm tech)
typically the bottom 2 floors are taken for power scheme ( vcc and gnd specification)

as the number of floors increase the cost per floor (fabrication cost) increases drastically. and the aspect ratio also increases.. thickness of the floor also increases.. some aspects such as frinjin capacitance and de couplin capacitance shud be taken into consideration.. the resistance of the top layers would be lesser than the bottom layers.
routing is done between the standard blocks and the designed blocks through the top most layers.

Step 7 - Circuit extraction -- this is done on decidin the amount of resistive capacitance on each of the wires.. this is very important as it takes care of signal integrity.
there is no capacitance as such n the ckt.. there is only capacitance which acts as a load to regulate the amt of current flow through the wires..and there by helps to avoid conditions like Electromagnetic inteference/cross talk/reflection/transmission/signal degradation/ or other notable signal integrity issues.

the steps 4,5,6,7 are post layout simulations

here in MAGMA design automation tool.. u wud get a LEF/DEF format.. this is actually a dummy format which doesnt have any information abt the mos layers..
by importing the TSMC library ( pay and buy it) u can get another format which is the GDSII .. this has all information including the information on the mos layers, this is the file which is necessery for actualy fabrication.

the intermediate file formats for netlist and others are DB(database format - typically CDB cadence database)

all synthesis/simulations for design is first implemented on FPGA -- target device and checked for functionality and faults .. then after which final implementation of ASIC is done.. (either on fully custom or semi custom ASICs)

hope this helps you.. if u have any doubt plz do post a reply.. i shall get some clarifications

with regards,

the physical synthesis perform after the floorplan.
however, you can also use phsycal compiler to synthesize the RTL to gates by specifying some "estimated" physical information.

i think that physical compiler have two ways to implement the physical synthesis.
RTL---Netlist(from pc,pc have same logic synthesis engine with dc)-----Physical synthesis optimize.
another way
Netlist(from dc)-----Physical synthesis optimize

Hi, JesseKing

You might read the <Advanced ASIC Chip Synthesis> 2nd. In the Chapter 10, the book compare the DC and PC.

Physical synthesis can be performed using the following two modes:
1.RTL to Placed Gates (or RTL2PG)
2.Gates to Placed Gates (or G2PG)

PC includes the DC.


If you use the new tool of Synopsys' Physical Complier: IC Complier, you have to re-build the compling flow with IC Complier's command.


Good Luck

Hi everybody
physical synthesis flow from Arunragavan was very infomative.Thanku Arun

The design flow belong to MAGMA design automation tool.. each tool has its own design flow.. ISE has it own flow.. umm i guess it wud be better if u can go thru each tool's own website to findout better in depth abt their design flows!

with regards

is there any workshop of Psyn ?find answer from user guaid and quick ref is so complex,replily .

I cannot speak about Synopsys in particular but the DEF format is very general. A valid DEF can have as little information - only Core area +rows defined or as much information as placed cells and routing. One can a create a basic DEF file by reading into a physical synthesis tool the following -

1. Synthesizable RTL (.v, .vhdl)
2. Library .lib
3. Library .LEF
Optional
4. aspect ratio of chip (default=1) and utilization % (default = 85%).

The above info is enough for floorplan. You can write out a DEF (or PDEF) and use this DEF/PDEF as a input file for subsequent part of the physical synthesis flow - for example placement, timing optimization ..etc.