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[SOLVED] How does VCO output the locked on frequency once the error voltage is zero?

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Hi All,

From my understanding of a VCO if no voltage is applied the VCO will output its free running or quiescent frequency. If the VCO frequency is locked on which then causes the phase detector to output 0V, is it the capacitor of the low pass filter that retains the previous control voltage to achieve and hence sustain the output frequency for a lock?

Thanks in advance!

PLL diagram:

http://members.chello.nl/~m.heijligers/DAChtml/PLL/PLL1-1.gif
 

your sequence is corrupted. When the output of the vco is at the intended frequency and phase, the two inputs of the pfd are inphase and hence the output of the pfd is not zero, it is a square signal of 50% duty cycle. This signal is directed to the charge pump and the output of the charge pump is filtered by the low pass filter to give the dc value corresponding to the frequency of interest.
 
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    FvM

    FvM

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I presume you "no voltage is applied" means no input to the PLL phase detector rather than "no voltage applied to the VCO".

Secondly, VCO input isn't generally zero in locked state, it's the voltage required to set the locked frequency. It should be noted that your schematic isn't very detailed. There's usually an integrator (often implemented as charge pump) between phase- respectively phase-frequency detector. In locked state, the PFD output can be zero while the integrator maintains a non-zero VCO input. Review a text book!
 
Hi FvM, thanks for your reply.

I meant what I said. If the phase detector has input signals in phase, it's from my understanding that the output would be 0V to the low pass filter which is shown in the diagram. My question was whether the capacitor in this filter maintained the VCO input required for the output frequency which you have confirmed. I have consulted text books, many in f
 

As said, the input to the low-pass filter in not zero in locked state. The input to the charge pump or integrator is. Your schematic is too simplified, this is better https://en.wikipedia.org/wiki/Phase-locked_loop#Block_diagram

PLLs can be build without an integrator, but they have a non-zero phase difference in locked state. Example: CD4046 using phase comparator 1 or 2.
 
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