current mirror layout

Hi trying to do the layout for of a current mirror part of the circuit with 3 transistors. The transistor dimensions for the three are W=1u and L=180n, second W=700n and L=180n and for the third W=700n and L=180n...The second and third are the same but the first one Width is little higher. current mirror requires well matching but the reason behind choosing the other two to be W=700n was becoz say a current of 30nA wanted to be copied from 1st to second and third the current copied was more than 30nA if the 2nd and 3rd width were kept to 1u. So width for both were reduced so they copy exactly around 30nA and not more. First of all is it wrong to do this??? becoz isnt the ultimate aim to copy 30nA in all 3 transistors. It is fine for simulation but for layout will this be a problem??? because even if transistors are well laid out with same dimensions problems occur during fabrication. So will this cause any problem if usage of 1u and 700n for 2nd and 3rd but follow other design rules like proper spacing is followed. Also if it does occur can anyone kindly suggest how to make the layout for these 3 transistors. Like how to lay them out by splitting them or to combine them. Any possible way that would be correct for the case pls help. Thank you!!!!

Step the transistors with the 1u in between the other two.

Oh thank you so much for the help. Previously those 3 transistors was made to 2 as in the 1u was laid seperately and the 700u tranistors were combined using fingers since they shared the same source. so it was like
drain gate source(shared of two 700u ones) and gate drain... Like this. But i guess the suggestion is to seperate these two and place the 1u transistor inbetween these both. can you please explain me how this will make a difference. Is it because the transistors will see the same neighboring 1u to the left and right of them. Also i got one more suggestion saying to increase all the length of the 3 transistors from 180n to 1u.... Could you kindly explain how this also would make matching good??? Thanks again!!!

Also could you please tell if building a current mirror with different tranistor dimension is a correct thing to do??? Because so far everything found related to current mirrors was mentioned to have the same dimensions.. But what is the point of maintaining that if we are not able to copy the desired same current. Why can't the other transistors be adjusted to the get the required current even if they are different. It is understandable that the dimensions is mainly during errors that may occur during fabrication but pls can anyone let me know in general is this a wrong way????

well, i think requirement for same dimension start with the "matching" word, since current mirror is required. That matching require layout devices should have same characteristics of systematic factors like STR stress, well proximity... and other factors during fabrication. So different dimension will break that "matching".

anyway, in you case, i think you can try that w=1u, nf=1 to w=0.5u, nf=2 and place between those 0.7u, share terminal if posible, fill middle deadspace made 0.5u by diffusion layer, and adding 2 side dummy for better.

Sorry for my bad English.

Sorry i don't get it a little. So you are suggesting to place the W=1u transitor inbetween the two W=700n transistors?? What did you mean by "you can try that w=1u, nf=1 to w=0.5u, nf=2"....Wer does a 0.5 transistor come here??? Pls let me know... And so it should be like below way
............dummy, 700n, 1u,700n, dummy..... Also i have never used dummy... suppose say i make a dummy transistor... Wer am i supposed to connect the dummy transistors gate, drain, source and bulk???? because say if i connect source to gnd and gate to a voltage won't the dummy affect my circuit reult??? can anyone pls give me some simple links about dummy???

Also wat does this mean"fill middle deadspace made 0.5u by diffusion layer".... wat do you refer to as in middle space????? And should i add another W=0.5u transistor... Finally can you kindly answer is it wrong practice to use current mirror with different dimensions but we have them matched?? Is it fine then???

i'm sorry for my unclear word .

I don't know your circuit, so i will assume those 3 having same source. So your arrange will be somehow like:
S|0.7u|D D|1u|S D|0.7u|S (S/D are source/drain)

so my idea will be:
S|dummy|D|0.7u|S|0.5u|D|0.5u|S|0.7u|D|dummy|S

I will split 1u width, 1 finger transitor to 0.5u width, 2 fingers transistor, sharing source for our 3 active transistors.
About the dummy, actually, adding them will help you layout result closer to circuit result. As you know, thing on silicon will be different with your layout, in this case, Vth of 0.7u transistor will be different with your design due to systematic factors such as STI stress,... or due to etching step in fabrication. So adding side dummy will help you minimize these effects. If you worry about coupling, you can see there is no different of Cdb or Cdg of 0.7u transistor.
About connection of dummy, since transistor is operated by voltage, you just tie its gate to vdd (if pmos) or vss (if nmos) for deactivate it (just like how inverter works). Sharing terminal of dummy with your active transistor for eliminating STI area at the side of active transistor.
About "fill middle deadspace made 0.5u by diffusion layer", as you can see in my placement, there will be a little STI deadspace above 0.5u, 2 finger transistor. You can reduce unexpected effect caused by this area by fill in diffusion layer (the one create source/drain), connect it with vdd/vss (depend on your bulk connection).

about the different dimensions thing, honestly, I've not seen any matching part with different dimension up till now. And in my opinion, you can't get devices having matched characteristics when they have different dimensions if you applied systematic effects or other effects in real silicon. Even some foundry like TSMC or Samsung recommend use same dimensions for matching devices in their design manual.

I think you should study on cmos systematic effect, and random effects... (might be a little cmos fabrication for more understanding why these effects happen), then apply on you layout, you won't be confuse anymore.

preethi19 said:

current mirror requires well matching but the reason behind choosing the other two to be W=700n was becoz say a current of 30nA wanted to be copied from 1st to second and third the current copied was more than 30nA if the 2nd and 3rd width were kept to 1u. So width for both were reduced so they copy exactly around 30nA and not more. First of all is it wrong to do this??? becoz isnt the ultimate aim to copy 30nA in all 3 transistors.

Click to expand...

This surely can be done, but actually this isn't the right way to make current mirrors: in schematic analysis, the current mirror currents for the same W/L would be identical if all the mirror MOSFETs would have the same Vds. Apparently, this isn't the case in your design. So what you did by reducing W is "corriger la fortune", but this works only if you can assure that the 2^nd and 3^rd mirror MOSFETs always keep their same Vds.

It is possible to use longer MOSFETs or more complex current mirrors which are less dependent on Vds, or to guarantee the same Vds for all mirror MOSFETs by design, but this usually needs the usage of an opAmp.

Be aware that layout might create more current variation, so be sure to use very good symmetry plus dummies, as lazybear suggested.