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scan insertion is something which is an obsolete idea when the tools didn't handle scan during normal synthesis. One used to synthesize the Verilog netlist with non-scannable flops. then the flops were replaced by their scan versions (scan insertion)...and connect the scan_in,scan_en etc. This was older way of things. these days the tools take in scan-flops and do the optimization which is scan synthesis ( optimizing the scan chain also along with the logic). scan insertion is an older and obsolete concept.
one optimization is how the scan is stitched in such a way that the timing is met. You can connect scan chain for flop A-> B -> C or C->B->A.....one of them will be better for placement or timing. The tool optimizes for the placement and timing. logic optimization. ...suppose Q is connected to sin of the flop...you can as well use the logic after Q and take the signal which is derived from Q into the sin so that hold buffers are not added and you can use the logic itself to take care of the hold ...there are others but in simple terms scan is treated like any other signal and optimized....
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