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[SOLVED] Does anyone knows what how to handle colck gating?

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u24c02

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Hi

i just want to implement global clock gating.
for example the following code.
But The problem is that global clock gating is not well implement.
My intend is that INC0,INC1,INC2 is working as global clocking.
But The result is not well implement in my intend.

So i wnat to know how am i do for global clock gating implementation ?


Code: 
module counter (CLK, RESET_, INC0,INC1,INC2, COUNT);
input CLK;
input RESET_;
input INC0;
input INC1;
input INC2;
output [2:0] COUNT;
reg [2:0] COUNT;
...
...

wire ck0;
wire ck1;
wire ck2;

assign ck0 = clk && INC0;
assign ck1 = clk && INC1;
assign ck2 = clk && INC2;

block_1 u_block1(
.clk (clk),
.en (ck0),
...
...
)

block_2 u_block2(
.clk (clk),
.en (ck1),
...
...
)

block_3 u_block3(
.clk (clk),
.en (ck2),
...
...
)


...
...

endmodule
 
Last edited by a moderator:

Hi ,

YOu should try as below

Code: 
module counter ( .....

...
...
input INC2;
output [2:0] COUNT;
reg [2:0] COUNT;
...
...
< Better to synchronized INCO0 in 'clk' domain before using in this module>>
CG_CELL_INSTNACE  U_CG_CELL_INSTANCE_1
(
.clk(clk),
.en(INC0),
.se(dft_scan_enable),
.out(ck0)
)
.
....
....


block_1 u_block1(
.clk(ck0)
.en(INC0)
..
..)

Try this.
 
Last edited by a moderator:

Oh good

This is what i want answer.

So did you mean that i have to adding inside each blocks?

- - - Updated - - -

Is that any problem in logic synthesis from design compiler?

[ COLOR="silver"]- - - Updated - - -[/COLOR]

I trying to synthesis clock gating cell instantiation method above design.
but the instanciated cell is gone in netlist.
Why not synthesised this ?
 
Last edited:

Hi u24c02,

You can add Clock Gating Cell in the Top Level or inside the individual blocks as well. It is better to add CG cells at the Top.

You said your Clock Gating Cells are being removed in the synthesis, check whether you have connected the Clock Gating Cell output properly or not
 
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