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Deterministic Results with Design Compiler

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ebrahimi.khoy

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I run synopsys design compiler for a relatively large processor core and every time I get a different netlist. Is there any why to get deterministic results from this tool?
 

Normaly if you have the same constraints, the same rtl code, the same tool version and the same script, you should have the save netlist.
 

This is not true for Design compiler. I guess they implemented an stopping condition based on the time. Since the timing is dependent on the other running tasks, it become non-deterministic.
 

The results need not be deterministic. The tool uses a random seed every time.
 

The amazing thing is how few designers really understand this behaviour. I heard a talk in a eda conference where the researcher did multiple compiles
of the same logic and saw results vary by up to 10%.

John Eaton
 
jt_eaton said:
The amazing thing is how few designers really understand this behaviour. I heard a talk in a eda conference where the researcher did multiple compiles
of the same logic and saw results vary by up to 10%.

John Eaton
Click to expand...

Do you remember the paper title for that presentation?
 

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