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Comparator challenge (FPGA)

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Godup

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Hello frndz,
Again, i want to design a comparator that can compare two analog voltage (e.g 3.0v and 1.5v) for a STRATIX III FPGA. Meaning my design is supposed to be digital using VHDL. The comparator is should be sensitive to the input analog voltage such that voltage 3.0 to 2.5 = HIGH (1) and 2.0 to 1.5 = LOW (0) (My DE 3 board has the capacity to adjust the input voltage to the above voltage levels). Can this be done in VHDL??? and how it done???
 

On fpga you can use/abuse differential inputs as comparator, but you would have to read the docs for the IO's on that specific fpga to make sure it will do everything you need.
 

mrflibble said:
On fpga you can use/abuse differential inputs as comparator
Click to expand...
.
Saw something like that on the pin planner. an icon (differential pin pair), is that what u meant by differential input??? some where labelled "DQ" and some labelled "DQS". Does assigning analog voltage with different voltage level (e.g 1.0v and 3.0v) cause the comparator sense voltage difference?

- - - Updated - - -

mrflibble said:
On fpga you can use/abuse differential inputs as comparator
Click to expand...
.
Saw something like that on the pin planner. an icon (differential pin pair), is that what u meant by differential input??? some where labelled "DQ" and some labelled "DQS". Does assigning analog voltage with different voltage level (e.g 1.0v and 3.0v) cause the comparator sense voltage difference?
 

Godup said:
Saw something like that on the pin planner. an icon (differential pin pair), is that what u meant by differential input???
Click to expand...
Those are the ones I mean yes.

Does assigning analog voltage with different voltage level (e.g 1.0v and 3.0v) cause the comparator sense voltage difference?
Click to expand...
Yep.
 

mrflibble said:
Yep.
Click to expand...

In time past i had encounter with the "differential pin pair"... "DQ" were mapped with "DQ" and "DQ" were mapped with "DQS". Where mapping such as (DQ & DQS) both came up HIGH when either of them are assigned as output pin and vise versa. Though not so with same mapping (DQ & DQ). Which one of the mappings would respond to voltage difference???
 

I fear the question is phrased so unclear that any answer runs at risk to misunderstand it...

You know that most FPGAs (also Stratix III) has pairs of input pins that can be configured as LVDS receivers. By specification they compare the voltage at the respective n and p pins of the pin pair, the common mode range is however limited (0.05 to 1.85 V), differential threshold and offset are guaranteed to keep the requirements of the LVDS standard, but nothing more.

You'll possibly observe that individual FPGAs have acceptable comparator behaviour (I never tried), but this won't tell anything about expectable type variations.
 

Godup said:
Which one of the mappings would respond to voltage difference???
Click to expand...

I have no idea what that means. Maybe it would help if you read the datasheet for the differential IO standars for your fpga. For one, because that way you will find out what limitations are there (as for LVDS as FvM pointed out). Incidentally, you can bias and scale the input voltages by adding voltages at the node, same way you would do for an opamp. See this link for an example of what I mean.
 

Hello, still designing a comparator (VHDL) and i want to assign an input pin with a fixed gain/ref (e.g 00001100). How am i supposed to assigned this width to the FPGA??? Is it compulsory i attach a daughter board (DDR memory) and assign this data to it or i can simply pick any of the traditional mother board pins for assignment???
 

Hi Godup,
I could not understand your requirements correctly.
FPGA is a digital device.
In addition to CMOS inputs, it has the ability to receive LVDS signals, which are also Digital.
If you just want to coursely segregate the signal (compare), you can trick the system by providing analog signal.
The input will be taken as 0 or 1, which you can process.
But by doing so, you risk getting the input in intermediate state, when high current flow through the lines.
Here I am confused with your amplification requirement.
In this case, you will need an ADC, which is not a component of FPGA.
 
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