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help in project needed

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Shyam Joe

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the following is my coding for a module while checking syntax i found the following errors
ERROR:HDLCompilers:26 - "fpunit.v" line 29 unexpected token: 'parallelreg'
ERROR:HDLCompilers:26 - "fpunit.v" line 29 expecting 'IDENTIFIER', found '256'
ERROR:HDLCompilers:26 - "fpunit.v" line 29 expecting 'IDENTIFIER', found '1'
Module <fpunit> compiled
ERROR:HDLCompilers:26 - "fpunit.v" line 31 expecting 'endmodule', found 'for'
plz help me to solve dis
Code: 
module fpunit(p,co,clk,a,b);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
wire c1,c2,c3,c4;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [256:0] v1,w1,v2,w2
parallelreg a1(s1,256'b0,clk,1'b1);
parallelreg a2(s2,256'b0,clk,1'b1);
for(i=255;i>=0;i=i-1)
begin
muxb a3(u,s1,s2,b[i]);
flp a4(v1,u);
notb a5(s3,s2);
muxb a6(s4,s1,s3,co);
bitadd a7(v2,s1,s4,c0);
notg a8(c3,co);
notb a9(s5,p);
muxb a10(s6,p,s5,c3);
bitadd a12(w1,v1,s6,1'b1);
bitadd a11(w2,v2,s6,c3);
org a12(c1,w1[256],v1[256]);
org a13(c4,w2[256],v2[256]);
muxg a14(c2,v2[256],c4,c3);
muxb a15(t1,w1[255:0],v1[255:0],c1);
muxb a16(t2,w2[255:0],v2[255:0],c2);
muxb a17(a,t1,t2,b[i]);
muxb a18(b,t2,t1,b[i]);
parallelreg a19(s1,a,clk,1'b0);
parallelreg a20(s2,b,clk,1'b0);
end
endmodule

- - - Updated - - -

i hav attached my sub module codings and block dig of my module
 

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  • project.doc
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  • block dig.doc
    198.5 KB · Views: 68

also your parallelre mapping doesn't make sense...
 

rberek said:
You forgot a semi-colon at the end of this line:
r.b.
Click to expand...
thanks. the other errors are cleared. but this error still exists "expecting 'endmodule', found 'for' "what to do??
 

IIRC, you can't have a for loop outisde of an initial or always block or similar. In your case, where you are using it to save typing when you are instantiating many modules (that's why you are using it, right?) then you should use encase the for loop inside a Verilog generate statement.

r.b.
 

when i use dis code i got dis error "ERROR:HDLCompilers:26 - "fpunit.v" line 32 expecting 'endmodule', found 'for' "

Code: 
module fpunit(p,co,clk,a,b);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
integer i;
wire c1,c2,c3,c4;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [256:0] v1,w1,v2,w2;
parallelreg a1(s1,256'b0,clk,1'b1);
parallelreg a2(s2,256'b0,clk,1'b1);
for(i=255;i>=0;i=i-1)
begin
muxb a3(u,s1,s2,b[i]);
flp a4(v1,u);
notb a5(s3,s2);
muxb a6(s4,s1,s3,co);
bitadd a7(v2,s1,s4,co);
notg a8(c3,co);
notb a9(s5,p);
muxb a10(s6,p,s5,c3);
bitadd a12(w1,v1,s6,1'b1);
bitadd a11(w2,v2,s6,c3);
org a12(c1,w1[256],v1[256]);
org a13(c4,w2[256],v2[256]);
muxg a14(c2,v2[256],c4,c3);
muxb a15(t1,w1[255:0],v1[255:0],c1);
muxb a16(t2,w2[255:0],v2[255:0],c2);
muxb a17(a,t1,t2,b[i]);
muxb a18(b,t2,t1,b[i]);
parallelreg a19(s1,a,clk,1'b0);
parallelreg a20(s2,b,clk,1'b0);
end
endmodule
But when i modify it as lik dis i got dis errors
"ERROR:HDLCompilers:26 - "fpunit.v" line 35 unexpected token: 'muxb'
ERROR:HDLCompilers:26 - "fpunit.v" line 36 unexpected token: 'flp'
ERROR:HDLCompilers:26 - "fpunit.v" line 37 unexpected token: 'notb'
ERROR:HDLCompilers:26 - "fpunit.v" line 38 unexpected token: 'muxb'
ERROR:HDLCompilers:26 - "fpunit.v" line 39 unexpected token: 'bitadd'
ERROR:HDLCompilers:26 - "fpunit.v" line 40 unexpected token: 'notg'
ERROR:HDLCompilers:26 - "fpunit.v" line 41 unexpected token: 'notb'
ERROR:HDLCompilers:26 - "fpunit.v" line 42 unexpected token: 'muxb'
ERROR:HDLCompilers:26 - "fpunit.v" line 43 unexpected token: 'bitadd'
ERROR:HDLCompilers:26 - "fpunit.v" line 44 unexpected token: 'bitadd'
ERROR:HDLCompilers:26 - "fpunit.v" line 45 unexpected token: 'org'
ERROR:HDLCompilers:26 - "fpunit.v" line 46 unexpected token: 'org'
ERROR:HDLCompilers:26 - "fpunit.v" line 47 unexpected token: 'muxg'
ERROR:HDLCompilers:26 - "fpunit.v" line 48 unexpected token: 'muxb'
ERROR:HDLCompilers:26 - "fpunit.v" line 49 unexpected token: 'muxb'
ERROR:HDLCompilers:26 - "fpunit.v" line 50 unexpected token: 'muxb'
ERROR:HDLCompilers:26 - "fpunit.v" line 51 unexpected token: 'muxb'
ERROR:HDLCompilers:26 - "fpunit.v" line 52 unexpected token: 'parallelreg'
ERROR:HDLCompilers:26 - "fpunit.v" line 53 unexpected token: 'parallelreg' "
Code: 
module fpunit(p,co,clk,a,b);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
integer i;
wire c1,c2,c3,c4;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [256:0] v1,w1,v2,w2;
parallelreg a1(s1,256'b0,clk,1'b1);
parallelreg a2(s2,256'b0,clk,1'b1);
initial begin
for(i=255;i>=0;i=i-1)
begin
muxb a3(u,s1,s2,b[i]);
flp a4(v1,u);
notb a5(s3,s2);
muxb a6(s4,s1,s3,co);
bitadd a7(v2,s1,s4,co);
notg a8(c3,co);
notb a9(s5,p);
muxb a10(s6,p,s5,c3);
bitadd a12(w1,v1,s6,1'b1);
bitadd a11(w2,v2,s6,c3);
org a12(c1,w1[256],v1[256]);
org a13(c4,w2[256],v2[256]);
muxg a14(c2,v2[256],c4,c3);
muxb a15(t1,w1[255:0],v1[255:0],c1);
muxb a16(t2,w2[255:0],v2[255:0],c2);
muxb a17(a,t1,t2,b[i]);
muxb a18(b,t2,t1,b[i]);
parallelreg a19(s1,a,clk,1'b0);
parallelreg a20(s2,b,clk,1'b0);
end
end
endmodule
Hw 2 solve it
 

Your post is very confusing.

You have two chunks of code in it. You imply that the errors are for the second chunk of code but the errors refer to line numbers up to 53 and the second chunk of code is only 36 lines.

Also

1) You cannot put module instantiations in initial and always blocks. Instantiations using for loops need to be in generate blocks, as I previously mentioned.

2) You are doing odd things in your instantiation loop. You have several instantiations in your for loop that do not make use of the loop variable (i). That means you will instantiate the exact same thing, with the exact same name, 256 times. This is redundant and Verilog will only use one of them.

3) The instantiations that do make use of the loop variable (and there are not many of those) will be instantiated 256 times but with exactly the same name. Verilog will only use the last instantiation of that module.

The generate/for loop combo is only a way to save typing. Is is executed at compile time, not run time. Why are you instantiating so many identical modules?

r.b.
 
Last edited:

i need all the instances to be executed 256 times. every instance is getting a signal from previous instance. when i use generate statement & modify the code as lik dis
Code: 
module fpunit(p,co,clk,a,b);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
integer i;
wire c1,c2,c3,c4;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [256:0] v1,w1,v2,w2;
parallelreg a1(s1,256'b0,clk,1'b1);
parallelreg a2(s2,256'b0,clk,1'b1);
generate
for(i=255;i>=0;i=i-1)
begin
muxb a3(u,s1,s2,b[i]);
flp a4(v1,u);
notb a5(s3,s2);
muxb a6(s4,s1,s3,co);
bitadd a7(v2,s1,s4,co);
notg a8(c3,co);
notb a9(s5,p);
muxb a10(s6,p,s5,c3);
bitadd a12(w1,v1,s6,1'b1);
bitadd a13(w2,v2,s6,c3);
org a14(c1,w1[256],v1[256]);
org a15(c4,w2[256],v2[256]);
muxg a16(c2,v2[256],c4,c3);
muxb a17(t1,w1[255:0],v1[255:0],c1);
muxb a18(t2,w2[255:0],v2[255:0],c2);
muxb a19(a,t1,t2,b[i]);
muxb a20(b,t2,t1,b[i]);
parallelreg a21(s1,a,clk,1'b0);
parallelreg a22(s2,b,clk,1'b0);
end
endgenerate
endmodule
i got dis error
ERROR:HDLCompilers:297 - "fpunit.v" line 34 Generated begin-end blocks must be named
ERROR:HDLCompilers:27 - "fpunit.v" line 34 Illegal redeclaration of ''
plz correct dis
 

You need to add a name to your generate block

PS. the way you talk about modules being "executed", it sounds like you think a module is a function call from C. This is a very bad way to think. Modules exist all the time. think of a module like a chip on a circuit board - it cannot be added and removed as and when you want it - its there and running all the time.
 

What TrickDicky said.

As well, you will need to add

Code: 
   genvar i;

to define the loop variable.

Then to paraphrase and add to TrickyDicky's remarks. You do seem to think that what is going to happen is that the code will first "execute" muxb a3(u,s1,s2,b) and then "execute" flp a4(v1,u), etc, and then when you get to the bottom of the loop, you will repeat this execution. Nothing could be farther from the truth. Verilog is not a procedural language and modules are not functions. This is a hardware description language.

All you are doing by instantiating a module is equivalent to placing a chip on a board or drawing it on a schematic. You are describing how the modules are interconnected, nothing more. All the modules operate in parallel all the time.

If something has to happen 256 times and the results are passed from module to module, then each module must have RTL that describes circuitry which receives data, performs some operation, passes data out of the module and repeats that 256 times. You will have to look at your overall system and make sure that the data gets passed at the right time and that each module knows when it is getting new valid data.

For loops are really only used in behavioural coding, testbenches and in generate blocks. Generate blocks are used to save you typing in cases where there are lots of repetitive statements. The for loops are not really used as they are in C.

You might want to find a good Verilog book or on-line tutorial and familiarize yourself with module instantiation and the whole premise of hardware description languages. If you have a software background they will really confuse you at the start.

r.b.
 

As u have said i placed the module instances that do not use the loop variable (i) outside the for loop.when i check for syntax in xilinx it shows no error.but when i simulate it using modelsim it gives this error
ERROR: fpunit.v(27): near ";": expecting: '('
ERROR: fpunit.v(34): near "end":syntax error
ERROR: C:/Modeltech_5.5e/win32pe/vlog failed

and here is my coding
Code: 
module fpunit(p,co,clk,a,b);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
wire c1,c2,c3,c4;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [256:0] v1,w1,v2,w2;
parallelreg a1(s1,256'b0,clk,1'b1);
parallelreg a2(s2,256'b0,clk,1'b1);
flp a4(v1,u);
notb a5(s3,s2);
muxb a6(s4,s1,s3,co);
bitadd a7(v2,s1,s4,co);
notg a8(c3,co);
notb a9(s5,p);
muxb a10(s6,p,s5,c3);
bitadd a12(w1,v1,s6,1'b1);
bitadd a13(w2,v2,s6,c3);
org a14(c1,w1[256],v1[256]);
org a15(c4,w2[256],v2[256]);
muxg a16(c2,v2[256],c4,c3);
muxb a17(t1,w1[255:0],v1[255:0],c1);
muxb a18(t2,w2[255:0],v2[255:0],c2);
parallelreg a21(s1,a,clk,1'b0);
parallelreg a22(s2,b,clk,1'b0);
genvar i;
generate
for(i=255;i>=0;i=i-1)
begin: ABC
muxb a3(u,s1,s2,b[i]);
muxb a19(a,t1,t2,b[i]);
muxb a20(b,t2,t1,b[i]);
end
endgenerate
endmodule
 

I do not see an issue with your code. I compared your generate structure to a piece of known working code and I did not see any problems. I cannot explain your modelsim issue, unless there is a typo hiding somewhere.

Also, you will still have an issue with your generate statement. You will create 256 instances named a3, 256 named a19 and 256 named a20. This is not legal. Every instance must have a unique name.

r.b.
 
What is typo actually??
Regarding instances do i not create 256 instances for a3,a19& a20
 

well, try to find it by yourselve. This is maybe the hardest way, but you will learn a lot.

Hint: divide et impera
 

Shyam Joe,

Once again you have a mis-match between your instance and the module definition (besides the other issues with the for loop).
parallelreg has defined the ports as din,clk,rst, and dout in that order, but you've connected it as parallelreg a19(s1,a,clk,1'b0);

So din = s1, clk = a, rst = clk, and dout = 1'b0

No, no, no, I'm certain that's not what you wanted.

Use named connections for all instantiated modules.

Regards
 
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