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I'm working on a project to design buffer. i have to set the w=180nm and L=180nm but in cadence 180nm technology i'm unble to do so please help me.. Thanks
I do not know that GPDK from cadence...
However, some technologies do not allow certain W and L configurations...simple as that.
Despite the node being "X"nm, that does not mean that every type of MOS in the technology can be as low as "X".
Sometimes it just has to be bigger than that.
Look at the Cadence Virtuoso CIW (main window) to check for any messages related to that.
It's unlikely that a "180nm" technology also has 180nm
(contact + 2*overlap) lithography. Contact and metal
always trail the most-challenging gate litho. The only
way is to make a "dogbone" FET which may not have
been qualified, may not be adequately controllable or
even doable outside a non-thin-film-SOI technology
where you can actually physically remove body that
is unwanted.
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