[SOLVED] Critical timing or circuit deisgn timing increased or affected. How and why?

Hi all,


my question is simple.
I have been wondering this and ofcourse what I think that if we have more combinational logic then the critical path increase.
But if we use if statements does critical path also increase (hence max freq. got decreased...?)

e.g.



which one is faster...
Or any other opinion for affecting critical path.

It is becuase I have been using toooo much if else statements and I have frankly less idea how to manage timings hence I am just coding any ways...

You have to think about what the if statemements are going to synthesise to - often they are muxes or clock enables. The way to increase the fmax is to break down the control statements and pipeline the design. You can never tell how much slower one bit of code will be other another because the synthesisor can often reduce the logic quite a bit. You need to look at the timing reports to see the slowest paths.

Yes
Critical path increases. As you know critical path is sum of all combinational paths. It means sum of : gate delays + wire delays + ...
By using if statement, in fact you are adding a multiplexer to your design. So the maximum freq. decreases.

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you are right dear TrickyDicky . But imagine the design has one path. So generally it increases the delay

syedshan said:

Hi all,
my question is simple.
I have been wondering this and ofcourse what I think that if we have more combinational logic then the critical path increase.
But if we use if statements does critical path also increase (hence max freq. got decreased...?)

e.g.

Code:

process(clk, rst)

begin
if(rst = '1') then

elsif (rising_edge(clk)) then
if(a=x and b=y and (c=p or d=q)) then
 bla bla bla...!
end if;

if(a=x) then
  if(b=y and (c=p or d=q)) then
   bla bla bla...

end if;
end process;

which one is faster...
Or any other opinion for affecting critical path.

It is becuase I have been using toooo much if else statements and I have frankly less idea how to manage timings hence I am just coding any ways...

Click to expand...

Your two example 'if' statements will synthesize to exactly the same thing.

While it is generally true that a long block of nested if statements will usually result in a large hunk of possibly slow synthesized logic, merely re-arranging as you have done to something that is logically the same will not change anything.

Kevin Jennings

Hello,

I also have a similar question. (sorry for I am not capturing the post).

1. While programming in HDL(VHDL/Verilog), how can we take care of the maximum frequency. and will the same code for two d/f/ FPGAs create different ckts having f/d clock frequency. For example I have an IP for ADC and I implement over Spartan 3 and other guy over virtex-6 while third guy over altera. WIll tge synthesizer adjust circuit distribution for appropriate clock frequency of the relevant fpga
2. Is there any particulars about programming method or language, i.e. Verilog is slower(in terms of max freq of ckt) in synthesizing ckt than VHDL, something like that...or system verilog is better than both...?

1. While programming in HDL(VHDL/Verilog), how can we take care of the maximum frequency.

Click to expand...

It depends on your coding skills. A better code decreases the delay.(And obviously increases frequency)

and will the same code for two d/f/ FPGAs create different ckts having f/d clock frequency. For example I have an IP for ADC and I implement over Spartan 3 and other guy over virtex-6 while third guy over altera. WIll tge synthesizer adjust circuit distribution for appropriate clock frequency of the relevant fpga

Click to expand...

It depends on your compiler's intelligence. A better compiler can reduce the amount of hardware. Also I wanna point to the technology of the FPGA. New FPGA with higher technology can reduce the delay.

2. Is there any particulars about programming method or language, i.e. Verilog is slower(in terms of max freq of ckt) in synthesizing ckt than VHDL, something like that...or system verilog is better than both...?

Click to expand...

I haven't seen anywhere that compare the languages in terms of speed. But I think it all depends on compiler as I said.

FixitFast said:

1. While programming in HDL(VHDL/Verilog), how can we take care of the maximum frequency. and will the same code for two d/f/ FPGAs create different ckts having f/d clock frequency. For example I have an IP for ADC and I implement over Spartan 3 and other guy over virtex-6 while third guy over altera. WIll tge synthesizer adjust circuit distribution for appropriate clock frequency of the relevant fpga

Click to expand...

The different technologies will affect timing as newer families tend to have faster routing. In addition, different fit seeds can also affect timing (ie. very minor changes to source code or the fitter seed in the project setting). But the best way to increase fmax will be to increase the pipelining. Setting good timing settings can also make the fitter work harder.

2. Is there any particulars about programming method or language, i.e. Verilog is slower(in terms of max freq of ckt) in synthesizing ckt than VHDL, something like that...or system verilog is better than both...?

Click to expand...

[/quote]

Source code choice will have minimal or no effect. It is the synthesised hardware that is important.

It depends on your coding skills. A better code decreases the delay.(And obviously increases frequency)

Click to expand...

That is exactly what I mean... By better coding design you mean

1. as less nested IFs as possible
2. pipelinings. ( I find it hard part, frankly)
3. avoid combinational ckts.
4. and...?

FixitFast said:

1. as less nested IFs as possible

Click to expand...

Kind of, but also not. The fitter may be able to place some of them well, and others not so well. If logic starts failing timing, you may have to pipeline it, or redesign it.

2. pipelinings. ( I find it hard part, frankly)

Click to expand...

THis will always be the hardesd bit.

3. avoid combinational ckts.
4. and...?

Click to expand...

Never use combinatorial clocks.

There are a large huge of amounts of tips that you can do to improve your design. Generally it increases the complexity and also increases the efficiency of the design.
If you are interested in digital design, I suggest you to read the : "RTL Hardware Design Using VHDL Coding for Efficiency, Portability, and Scalability" By PONG P.CHU.
I've read it and I can say it's an excellent book.