Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] doubts regarding RTL to GDS flow

Status
Not open for further replies.
Y

yuvraj7792

Newbie level 3
Joined
Mar 27, 2013
Messages
3
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,299
I am doing RTL to GDSII of a counter. I have written a code for it in VHDL. I am synthesizing it using Design compiler. While synthesizing, it is giving a warning for the unconnected outputs of the flipflops. I have left the Q_n output of some flipflops unconnected.
1.How to deal with such outputs?
2.what to do with such outputs while designing layout?
 

I have given "Logic 1" to the inputs of some flip flops. How to deal with such inputs in layout?
 

Usually, synthesis tool will pick up tiehi cell in your standard cell library to implement logic "1". You don't have to do anything special.
 
in general the logic 1 or 0 should be replaced by tie cell 1 or 0. Some technologies accepte to directly connect to the power net, but some other avoid that to respect the ERC.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top