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Whats the best way to implement this logic expression

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gtib007

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Hello there am using Virtuoso to draw a schematic and a layout of a certain expression and i want to know the best way to do it so i can optimise the speed of the transmission from each state.

the expression is OUTPUT = X + ( Y . (Z'))

shall i use de morgan theorem ? i will need two inverters if i do use de morgan theorem
and if i didnt i would still need 2 inverters, one to invert z and one to invert the final output value.

barring in mind i need to optimise the speed of the layout. so what do u suggest for the N and P MOS width sizing ?

Many thanks in advance !
 

What is the no of transistor you are using to implement this Expression?
 

Prashanthanilm said:
What is the no of transistor you are using to implement this Expression?
Click to expand...

10 transistors, 5 Pmos and 5 Nmos

2 Pmos and 2 Nmos to invert the Output and input Z

3 Pmos and 3 Nmos to implement the expression ..
 

I tried with different architecture, but it was of same 10 Transistors.
According to me , I think that in terms of Transistors it is optimum.

In order to determine the size of Transistors , you first have to get the value for Wn+Wp for cell height.
 

Prashanthanilm said:
I tried with different architecture, but it was of same 10 Transistors.
According to me , I think that in terms of Transistors it is optimum.

In order to determine the size of Transistors , you first have to get the value for Wn+Wp for cell height.
Click to expand...

What if i am driving a large external capacitor at the output ? what would my gate width be ?
 

It depends upon the architecture. You will choose the gate width depending on the outcome you want.

For Driving External cap, the widths are adjusted so that the delays are optimum.

For STD Cells, you do simulations on various of things like by varying Width, Length and Cap . And will conclude the optimum beta value after observing the results of simulation so that the delay difference is min.

Hope it helps!!
 
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