Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Clock domain problem

Status
Not open for further replies.
krishna2728

krishna2728

Member level 5
Joined
Oct 23, 2010
Messages
84
Helped
7
Reputation
14
Reaction score
6
Trophy points
1,298
Location
bengaluru,India
Activity points
1,734
I have a problem regarding usage of clock i am using a clock_2x (200Mhz) for manchester decoder and the output of this is driven to a SIPO which is using clk_x(100Mhz) How to avoid data synchronization problem between the two block
 

A small document called "crossing the Abyss: Asynchronous signals in synchronous world" , you can search in google.
This will gives you brief knowledge of clock domain crossing issues.

Do you want to synchronize serial data coming from 200MHz and perform manchester decoding or
you want synchronize the decoded data.

Basically handshake based or FIFO based synchronization schemes are used to transfer data from fast to slow clocks.
 
I suggest you to have a signal data_en in your manchester decoder. This signal will be used by SIPO to get data from decoder. Now synchronize data_en w.r.t clk_x using 2flops method and read data from FIFO using this data_en. FIFO will be written by decoder output @200MHz. So the reason to use data_en is to avoid synchronizing each data bit of decoder o/p.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top