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What's the best way to fix the constraint file when importing verilog modules?

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Elektronman

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Hello,
I'm working on a real time image elaboration project for the Atlys board (Spartan6-based). I use verilog and the Web ISE
Project Navigator.
I need to add support for UART communications, so that I can communicate (essentially send commands and receive status flags) with the Atlys board through a PC. I found a serial (UART) communication module based on the Picoblaze here: https://tristesse.org/pub/PicoBlazeDemo.zip . I'm trying to merge the module in my project.
In the demo there is a ucf file (ddscontrol.ucf) which has a name for the clock: NET "clk100" LOC = "L15"; which is different from mine
(my ucf has NET "clk" LOC = "L15";) So what is the best thing to do? Should I merge the two ucf files together and keep both lines,
or should I rename the clock? (clk to clk100 or clk100 to clk)?
Thank you
 

If this is the only conflict (which I somehow doubt :p ) then you can keep both ucf files, and then just keep one NET "clk" or "clk100". Which name you pick is really whatever is convenient for you. Which probably will turn out to be the name from joelby's code. Also, clk100 is a bit more descriptive, since it's the 100 MHz input on the Atlys board. So I'd keep that one.
 
G'day... Although coming from VHDL land, i may be able to shed some light... With your master clock, generally this will go straight into a a dedicated clock manager on the FPGA or at least a clk buffer to ensure it utilises the low skew clock routing fabric. From the manager the clock is routed out around the FPGA on a clock signal (or wire as I believe it is in Verilog). It is then just a matter of instantiating the UART as a module and port mapping it to the rest of the circuit. (This is the terminology and how it's done in VHDL, and I'm always confused as to how it's done in verilog, as there are a few ways..).... .

So in your design... clk is your the clock net inside the FPGA, (personally I would use a more descriptive name than clk as most projects have a number of clocks! so pehaps think about using clk100 if it's a 100Mhz clock) i've put togeather a quick example of how i think it would go... but please... i've never written verilog.. so it's only an example of how to route your clock.

Code: 
module rt_image(   //this is your top level... where you would constrain the phisical pins to the these ports.

    input wire clk,        <-- your clk net
    input wire ser_rx,
    output wire ser_tx,

    etc.....
    );


// UART
    wire    [7:0]    out_port;
    reg          en_16_x_baud;
    wire          write_to_uart;
    wire          tx_full;
    wire          tx_half_full;
    reg          read_from_uart;
    wire     [7:0]    rx_data;
    wire          rx_data_present;
    wire          rx_full;
    wire          rx_half_full;
    wire     [7:0]     uart_status_port;
    
    assign uart_status_port = {3'b000,rx_data_present,rx_full,rx_half_full,tx_full,tx_half_full};

    uart_tx transmit (
        .data_in(out_port),
        .write_buffer(write_to_uart),
        .reset_buffer(1'b0),
        .en_16_x_baud(en_16_x_baud),
        .serial_out(ser_tx),
        .buffer_full(tx_full),
        .buffer_half_full(tx_half_full),
        .clk(clk)); //.clk(clk100));        <-- note modded code here to connect you clk net to the Uart clk

    uart_rx receive (
        .serial_in(ser_rx),
        .data_out(rx_data),
        .read_buffer(read_from_uart),
        .reset_buffer(1'b0),
        .en_16_x_baud(en_16_x_baud),
        .buffer_data_present(rx_data_present),
        .buffer_full(rx_full),
        .buffer_half_full(rx_half_full),
        .clk(clk)); //.clk(clk100));        <-- note modded code here to connect you clk net to the Uart clk

then your UCF file should contain these constraints...

Code: 
NET "clk"  LOC = "L15";
NET "ser_rx"  LOC = "A16"; //obviously use the correct pin numbers....
NET "ser_tx"  LOC = "B16";

You would also need a simple state machine to drive everything... or you could drop the entire Picoblaze in and write assembler code (ewwww) to drive it!

Hope i've helped... but one point to note... I can't see how the clk signal is bought into the FPGAs dedicated clock routing resources? am I right in saying it isn't? I would expect to see this in the UCF file or by instantiating an IBUFG from within the code?

- - - Updated - - -

Sorry mrflibble... all credit to you for naming clocks appropriately.. you must have posted while I was still writing mine... i didn't see it...
 
thank you very much, that was really helpful! I will try to implement the UART interface ASAP; now I'm busy doing some tests on the board
 

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