Modelling MOSFET or Diff. pairs using VCCS

Hi,there!
I want to simplify my 5 mosfet amp which is consist of diff. pairs with resistor load.I heard that you can use VCCS to replace the input diff. pairs, and the ggain is set to the gm of the input transistor. I know the small signal current can be denoted as i=gm*vgs, then the VCCS can model the small signal current correctly.But,if there is only one VCCS with gm, what about the DC operating point? For the total current is not equal to gm*vgs but 0.5*u*C*(Vgs-Vth)^2. So,only using one VCCS,can it model the input differential pairs accurately?


Regards
urian

can you post the circuit for us to refer

- - - Updated - - -

if ciruits are parallel 1 Vcc is enough

hi,jeffrey,here is the schematic below:

urian said:

Hi,there!
I want to simplify my 5 mosfet amp which is consist of diff. pairs with resistor load.I heard that you can use VCCS to replace the input diff. pairs, and the ggain is set to the gm of the input transistor. I know the small signal current can be denoted as i=gm*vgs, then the VCCS can model the small signal current correctly.But,if there is only one VCCS with gm, what about the DC operating point? For the total current is not equal to gm*vgs but 0.5*u*C*(Vgs-Vth)^2. So,only using one VCCS,can it model the input differential pairs accurately?


Regards
urian

Click to expand...

Hi urian

The type of substitution you are performing to generate a simplified model basically works only if the circuit is guaranteed to operate within a limited region around the OP, you are basically linearizing the circuit. This is usually the case for circuits containing feedback. In your case you can set the correct output OP in several ways for example you can load the vccs with its output impedance (using a resistor) and a DC current source in parallel to the load. Also make sure there is a capacitive load on the output because infinite BW models tend to create convergence problems.

Hope this helps.

I just saw your schematic: since you already have loading resistors and you are keeping the circuit fully differential, you can just add DC current sources on both branches, just pick the right DC current to generate the correct DC OP but do not expect your model to exhibit a square law characteristic as you suggested in your opening post

Hi,dgnani.Thank you for your suggestion. I have modified my schematic as below:


This schematic is linearizing the diff.pairs around the one certain DC OP,which is provided by idc components, am I right?
And this simplification can't be used for modelling the practical circuit whose input can change within Vp-p, right?

Regards
urian

Hi urian

please notice a few points if you want to compare the two circuits in simulation:
MINOR
-) the real diff pair has no body connections - I am guessing you just forgot
-) looking into the inputs you see no capacitive load, which could create problem embedding this model in a real circuit - add at least Cgs in that case
-) the output impedance should have in parallel another resistor representing the output impedance of the diff pair - given your values this is probably negligible
-) this model in not good to analyze the negative supply rejection or common mode rejection

IMPORTANT
- your differential DC gain is extremely small (6 V/V), this will induce a significant systematic voltage offset even in closed loop configuration, this means a large OP contribution to the total bias current has to come from the vccs. Basically the two bias currents from the idc sources are not simply half of the tail current of the original opamp but they have to be sized ad-hoc to obtain the correct output OP voltage

Hi,dgnani,thank you for reply.Here is explanations:

-)Yes, the real schematic is just for illustration, so I dont draw completely.
-)This model is used to ideally modeling some portions of the circuit, then under this ideal circumstance, should I still add Cgs or something else to the input? Or if not, the model will make the rest of circuit work inproperly?
-)Yes,there should be a resistor accounting for output impedence of diff.pairs.And also can be neglected with the small res as you said.


Because the model is used for diff.pairs in a fold circuit whose fold factor is 3, the dc gain is small.The fold circuit and the complete model is as below:



just neglect the body effect.And I dont know whether it would neglect the capacitance also.This model is used for verification of digital correction and its accuracy is not important. I have set the min. current to zero and max. current of the six VCCS to the tail current.Should there be DC OP idc connected parallel with the VCCS as the simple diff.pairs before? I have set the all the ggain and res value to a appropriate value so the output of the model is about the same as the real circuit. I wonder whether this method is ok or not. Or may be I should use Verilog_A to model it?


Regars
urian

Hi urian

the addition of Cgs is necessary if you want AC analysis and perhaps TRAN (as long as you avoid large variations) to work properly. Without caps your circuit will have infinite bandwidth and will get into all sort of simulation problems and meaningless results. If you are just planning to run DC analysis of course caps do not matter...

the ggain of the vccs should be the gm of the real diff pair NFETs otherwise the DC gain will not be correct, the OP output voltage should be fixed otherwise and adding the idc in parallel is one option

current limiting the vccs can be quite tricky as there are quite a few versions of spectre that make a complete mess of the DC point when the limits are triggered. Assuming that your version will be able to handle it correctly your vccs should be able to generate currents of both signs (this is because -in your model schematic- vccs sources are modeling the combination of 2 NFETs rather than a single NFET...) so setting the minimum to 0 is not ok.

As far as I can tell there is no need for going to verilog-A models but I am not familiar with the circuit topology and application you are designing for; you would have to provide some more details if you want more insightful comments. In particular fold1.jpd does not make much sense to me: are those idc sources or vccs in that schematic?

Hi,dgnani,thanks again!

• This circuit is a folder of one stage with fold factor of 3 used in a three stage cascade fold-interpolating ADC. I only do tran analysis to see the tendency of digital calibration, so I want to simplify the circuit as much as possible to reduce the simulation time to a acceptable degree.
• If all of three stages are using the ideal model which we are discussing,then I think there is no bandwidth problem.So I dont add any cap in the model, am I right?
• The DC gain of diff.paris is around 4, and its absolute value is of no importance.When considering connect three model sequentially, I think the DC OP may be neglected in the middle stage, but the first and last must add idcs to ensure the circuit connecting to them have proper OP.
• I dont know the version of spectre will affect the result of VCCS bahavior, or I did not observe it.As in the 2nd pic, I use two VCCS branchs to model the diff.pairs, so in my option the VCCS need not generate current of both sign, but I am not sure of it.
• When refer to VerilogA, I think the concept can be expressed easily, but difficult to implement the details.

Regards
urian