DIY DSO using CPLD and SRAM--possible?

Most of the DSO designs Ive seen have a fast ADC feeding a FPGA (eg. KNJN Flashy--60-200MSPS). OTOH, eoscope uses a dual port FIFO to grab the ADC output from one port, and then uses a microcontroller to read those values at a slower rate from the other port. The problem here is that DIY-priced FIFOs are a bit slow (15ns). eoscope is restricted to 20MSPS.

OTOH, using a CPLD instead of a FPGA would be easier for a DIY project. But it is my understanding (may be wrong) that implementing memory (abt 128-512 bytes) in a CPLD is diffficult if not impossible.

Is it possible to use a fast (10ns) SRAM controlled by a CPLD to store the ADC output and then read the values into a PIC for processing? The CPLD would need to output successive addresses to the SRAM (at say 60MHz/100MHz) as well as the send the "Write" signal. The PIC would later read these addresses from the SRAM once enough samples have been obtained from the ADC.

I have only a beginners knowledge of CPLDs or FPGAs, so any input would be appreciated!

Thanks,
vkj

Yes, it's possible, but you might run in to I/O limitations if your ADC and memory both use lots of pins.

I would suggest that it's not that much more difficult to use a small FPGA than a CPLD. They come in hand-solderable TQFP packages and are much more capable. If you don't care too much about efficiency, you can use a few linear regulators if the FPGA requires multiple power rails. You'll then be able to use high speed ADCs that have differential (typically LVDS) outputs, which fewer CPLDs support. An FPGA might cost a little bit more, but because it'll include some fast RAM you will save a bit on BOM cost, board space, and PCB routing effort. How many samples are you thinking of storing, though?

It's probably best to start out with a development board. Once you're happy with the design, you can consider designing a standalone product, and by then you might have more of a feel for what you can do with an FPGA. By all means try out CPLDs too, though - you can get breakout boards for about $15 and they can be a fun way to get started (you'll need a programming adaptor, too).

Thanks for your reply.

My target is 60-100MSPS using an ADC08060/100. SInce I need 8 data bits and 512 bytes storage, there may not be a problem with the I/O pins. There will be two busses, data and address. The CPLD would use only the address bus to send the address as well as the WE signal. (Havent yet worked out the timing for WE tho.) The SRAM uses the address and data bus, as does the PIC which reads the data later for processing. The CPLD actually functions as a high speed mod-N counter (N=9). My concern is, given the complexity of the board, if this would work at 100MHz.

I would agree that the FPGA way is a most robust approach. And you hit on the very point that was bothering me: soldering the 100 pin package. Buying a dev. kit is a bit too expensive for me. Can you say which vendor's FPGA is the best for a beginner to start with? From the piont of view of (a) Ease of use of the dev. environment (b) size of the software to be downloaded (c) Any additional hardware to be purchased/made. Im assuing that the dev. env. is free?

Digikey lists the EP1C3T100C8N (100-pin TQFP) for $11. Thats quite affordable. There are other vendors listed for FPGAs: Atmel. Microsemi, etc.

Thanks,

vkj

Yes, it ought to be possible to do all of that with that ADC part and a CPLD. 100 MHz should be achievable as long as you're careful about signal integrity and perhaps pay some attention to PCB trace length matching.

A sample buffer of 512x8 would be no problem for even the smallest modern FPGA though. TQFP packages aren't too difficult to solder as long as you have a decent PCB with a solder mask. You might want to look at this list of cheap FPGA development boards. At 100 MHz I would recommend using a development board with a high speed I/O connector (from memory, all but the cheapest Digilent boards have Hirose or VHDCI connectors) or a custom board, as it can be tricky to get good results using 0.1" headers without many ground returns.

I only have personal experience with Xilinx but found their development environment reasonably straightforward after doing the ISE In-depth Tutorial. I imagine that all of the FPGA vendor tools are reasonably similar in quality, though Xilinx and Altera seem to have the majority of the market share and so you might find it easier to get help with them. The basic dev tools are free for low-end parts, and I think all of them are enormous to download.

If you're making your own board you probably want to get a JTAG programmer specific to the FPGA/CPLD vendor. Some development boards incorporate custom programmer software.

That was really useful. The point about using 0.1" headers at 100MHz is a bit of a downer since that is exactly what I was planning to do . Actually I find that the KNJN boards seem to use them at >100MHz. But hopefully, if I build my own board, I wont have to use a connector.

Thanks for the pointer to the tutorial. Seems quite readable. Digikey lists the cheapest Xilinx (Spartan 3A) part for $6, abt half of Altera's cheapest.

vkj

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That was really useful. The point about using 0.1" headers at 100MHz is a bit of a downer since that is exactly what I was planning to do . Actually I find that the KNJN boards seem to use them at >100MHz. But hopefully, if I build my own board, I wont have to use a connector.

Thanks for the pointer to the tutorial. Seems quite readable. Digikey lists the cheapest Xilinx (Spartan 3A) part for $6, abt half of Altera's cheapest.

vkj

Btw, personally I'd advise against the KNJN boards for people who are deeply interested in the design (i.e. most people on this site). The KNJN designs are missing the circuit diagrams (and I believe the FPGA source is missing for the oscilloscope too) - at least for the 'Flashy' boards which are the data aquisition boards for the FPGA. It is really annoying in my opinion, because it is a closed design, and very little information is given on the amplifier, and how the trigger function operates, and yet to me they look like development boards.

I haven't looked at the KNJN boards in detail recently. It's possible that you could get reliable 100 MHz transfers through a bad connector, but from personal experience with doing such a thing and wasting a lot of time, I would strongly advise against it. I would use a dev board and make my own add-on ADC board. When I was happy with that, and then if and only if I wanted to make lots of them, or if I wanted to do everything just for fun, would I try making a combined ADC-FPGA board.