The timing constrains are hard to reach when synthesizing!

wire load mode 안쓰는 방법

Hi, my friends.
Today i encounter a problem. When i synthesis a design, the timing constrains are difficultly reached. But i synthesis a subdesign, the timing constains is easily to reach. Why this happen?
The timing constrains setting for the subdesign are the same when i synthesis it independent or in the higher design.

flatten the design in synthesis

synopsys will choose a wireload model for you base on the design complexity, unless you specify otherwise. Your two synthesis sessions used different wireload models, check the first few lines of your timing report.

Re: A problem in synthesis!

You are wrong. My constrains are the same in two conditions. I think that it was cuased because too many subdesigns in my top design. The very paths of the subdesign maybe are not the critical paths when the subdesign in top design synthesis. So the synthesis results are not good as that of synthesising it alone.

Re: A problem in synthesis!

Have you tried to flaten the design before synthesis and do the optimization based on the flaten:ed design instead?

I assume you can do this and you do not have any guildlines for the floorplaner.

Would appreciate to see your comments,

BR,
/Farhad

Re: A problem in synthesis!

horzonbluz said:

You are wrong. My constrains are the same in two conditions. I think that it was cuased because too many subdesigns in my top design. The very paths of the subdesign maybe are not the critical paths when the subdesign in top design synthesis. So the synthesis results are not good as that of synthesising it alone.

Click to expand...

i am? do yourself a favor and think about what i said when you have huge timing violations in you post layout timing.

flatten a design, as stated above, is forcing the design to use a larger wlm. some ppl do use that as part of their flow.

Re: A problem in synthesis!

Hi, firewire2035.
Below is my report about my wire load model:
Wire Load: (use report_wire_load for more information)
wire_load_mode top
wire_load_model_max UMC18_Conservative
wire_load_model_min UMC18_Conservative

In two conditions, they are same. When i synthesis them, i always to use "set auto_wire_load_selection false" and appoint the wire load model.
And more, i alway use the top wire load mode. So i think we have considered the condition that you said. But i do not try to flatten my design. Have you good advices and experience about flatten design to reduce the area or improving timing?

A problem in synthesis!

i'd rather look at your timing report header, which show s which wireload mode is used while traversing the hierarchy. If the module is indeed forced to use only one wireload model, you will not be seeing wlm switching.

wire_load_mode top is correct. but if you are scripting this, consider the possbility of something is overwriting your env setup.

if you only see one wireload being used, then the next possibility is the fanout issue. generate a timing report w/ fanout and incremental timing on. look for large incr timing, and look at the driving cell and the fanout.

i can only give you my opinion, that is i like to flatten design @ a certain hierarchy for reasons you stated above. But many like to preserve hierarchy for future debugging purpose.