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unbonded output ports

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shaiko

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What is the state of output pins that aren't bond in the FPGA UCF file ?

some_output <= '1' ; -- "some_output" is defined as an output port in the top entity but not defined in the UCF file

What will happen ?
 
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I think the tool picks up a pin and assign the output signal to it (the pin for the best timing, I guess?).
 
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    shaiko

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yes, the tools will pick a spot at random. I really don't know who thought this was a good default, but it's what happens.
 
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I'm not sure about the exact algorithm it applies, but it can be useful if you're planning to design a circuit board and want to let the tools fit pins in optimal locations, which can help when there are slightly non-obvious constraints (such as half bank clocking regions, I/O buffer type and voltage restrictions, etc.). There's nothing worse than building a board and finding out too late that your design can't fit the pin placement you picked.
 
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You have option while generting the bitfile to decide about unconnected pins either to pull-up/pull-down or floating
 
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