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How to reduce FPGA kit clock speed?

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1nandha

1nandha

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I have to implement my VHDL code in a FPGA kit, the clock speed of the kit is 50hz which is very fast and i cant view my output with that speed, how to reduce the kit clock speed?
 

Re: To delay clock speed

you can use embedded PLL or DCM.
 
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    sntsh

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Re: To delay clock speed

Embedded PLL is using in Altera devices, but Pse tell me about DCM.
 

Re: To delay clock speed

DCM stands for "Digital Clock Manager" and is found in Xilinx device. It is digital PLL whose capability is not as robust as real analog pll, but it is capable of frequency division, frequency multiplication, synthesis, phase shift, etc.
 

Re: To delay clock speed

1nandha said:
I have to implement my VHDL code in a FPGA kit, the clock speed of the kit is 50hz which is very fast and i cant view my output with that speed, how to reduce the kit clock speed?
Click to expand...

First, You said very high speed, Did you really mean it is 50Hz? and 50MHz ?. I guess, 50Hz is not a high speed.
Second, what is your application\code logic and what type of output you get and how fast it is (In terms of freq) ?
 

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