[SOLVED] VHDL:problem with for-generate statement

Code VHDL - [expand]
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--Signals declarations are as follows:
 
    signal real_int,imag_int:mat3x8;
    signal i:int_1;
    signal j:ufixed (9 downto 0);
 
--data types are defined as follows:
 
  type my_array5 is array (0 to 7) of sfixed(7 downto -8) ;
  type mat3x8 is array (1 to 3) of my_array5;
 
--The error is in the following lines:
 
outer1:for a in 2 to 3 generate --stages after the first stage
        outer2:for b in 0 to (8/(2**a)-1) generate--b denotes the group that we are at now
          j<=to_ufixed(0.0,9,0);     --j is the power of the factor 'W',j=0 at the start of each group
          i<=b*(2**a);    --i is used to denote the index of the 1st element in each group
          inner:for k in 0 to ((2**a)/2)-1 generate --k determines the no of butterflyes in the current group
            for slice2:b_fly use entity work.b_fly(b_fly1);
              begin
                slice2:b_fly
                generic map(N1=>10,N3=>8)--N3=8 because it's 8-point fft
                port map(x_real=>real_int(a-1)(i+k),x_imag=>imag_int(a-1)(i+k),
                         y_real=>real_int(a-1,i+k+2**(a-1)),y_imag=>imag_int(a-1,i+k+2**(a-1)),
                         N=>a,
                         K=>ufixed(j),
                         z1_real=>real_int(a,i+k),z1_imag=>imag_int(a,i+k),
                         z2_real=>real_int(a,i+k+2**(a-1)),z2_imag=>imag_int(a,i+k+2**(a-1)));
                j<=j+1;
          end generate inner;
        end generate outer2;
      end generate outer1;