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[SOLVED] modelsim - error assertion causes file to open

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Is there a command line option to tell ModelSim not to open the .vhd/.v file when an failure assertion occurs, say from ending of a testbench?
 

You could try ending a testbench via event starvation (eg by stopping the clock)
But there is a setting (I had exactly the same thing) but I dont have modelsim at home - will check tomorrow at work.
 

thanks.

ya, it isn't a big deal, just annoying. i found another solution online, instead of asserting a failure at the end you can wait on a signal to assert from a .do file:

when -label sim_done {sim_done == '1'} {echo "Simulation finished."; stop;}
 

And heres how to do it:

Tools - Edit preference - By Name - source - Open on Break: Set it to '0' to disable window pop up.

As for killing a simulation, in VHDL I always have the following in my testbenches.

Code VHDL - [expand]
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------------------------------------------------------------------------------------------------
--clk_proc : process to generate the clock
------------------------------------------------------------------------------------------------
vid_clk_proc : process
  variable end_time       : time;
begin
  while not ENDSIM loop
    
    clk                    <= not clk;
    
    if NOW >= TIMEOUT*CLK_PERIOD then
      KILLSIM               <= true;
    end if;
    
    if run_clk then
      wait for CLK_PERIOD/2;
    else
      wait until run_clk;
    end if;
  end loop;
  
  if KILLSIM then
    report "Simulation Timed Out after " & integer'image(TIMEOUT) & " clock cycles."
      severity warning;
      
  else
    end_time := NOW;
    
    report "Simulation ended successfully after " & time'image(end_time)
      severity note;
      
  end if;
  
  wait;
end process;
 
--------------------------------------------------------------------
--Stop all processes to starve all events and stop the simulation
--------------------------------------------------------------------
ENDSIM <=    KILLSIM 
          or (input_complete and output_complete);


Then all testbench processes contain a loop like:

while not ENDSIM loop;

This way, I know all processes will die at the end of simulation, or if the testbench didnt complete successfully, or something has hung, it wont run forever because of the timeout.
 
thanks, thats a nice way to do it. little more graceful than just using an assertion as well.
 

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