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[DFT] How should functional Latches be handled during DFT/scan insertion?

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ivlsi

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Hello All,

[DFT] How should functional Latches be handled during DFT/scan insertion?

Thank you!
 

Any response? What about latches @ scan chains?
 
Hi.
It depends.
if you use LSSD design style for dft insertion, no need to do special things on latch, sams as normal flipflop
if you use mux design style for dft insertion, just make it transparent when doing dft. There is usually a TE pin for a latch cell.
You can tie it to Test Mode pin to make it controllable when doing test.
 
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