fypu
Newbie level 4
how to solve this problem?
"Error (10327): VHDL error at DU.vhd(51): can't determine definition of operator ""&"" -- found 0 possible definitions"
my VHDL code is:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
.
.
ALU_module: process (selP, selQ, P, Q)
variable sel: std_logic;
begin
sel := selP & selQ;
case sel is
when "00" => alu <= Q-P;
when "01" => alu <= Q - Q;
when "10" => alu <= P - P;
when others => alu <= P - Q;
end case;
end process ALU_module;
"Error (10327): VHDL error at DU.vhd(51): can't determine definition of operator ""&"" -- found 0 possible definitions"
my VHDL code is:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
.
.
ALU_module: process (selP, selQ, P, Q)
variable sel: std_logic;
begin
sel := selP & selQ;
case sel is
when "00" => alu <= Q-P;
when "01" => alu <= Q - Q;
when "10" => alu <= P - P;
when others => alu <= P - Q;
end case;
end process ALU_module;