Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by zyadzezo

  1. Z

    final steps to produce GDSII file for fabrication

    Dear all, I hope you are doing well. for first time i am implement layout with pex and lvs and DRC checks,now i want to put pads and continue fabrication process till tape out but i dont know anything about this steps,any recommendation any vedios any references i will appreciate your...
  2. Z

    PEX extraction erros

    i don't know how to get CIW transcript and i noticed that the cell map pin didn't appear
  3. Z

    PEX extraction erros

    I have a problem with running PEX in cadence with 130nm UMC each cell i run pex i have errors and warning with same number i have the pex file and running without issues
  4. Z

    [SOLVED] ERROR_during running LVS

    Thank you very much . i solved the problem as i found that MOM_Cap need to add special input files with technology
  5. Z

    MIMCAP_130MML130n connection

    i used calibare tool (mentor) on cadence virtuoso i am taking about metal layer which capacitor was built from. AL_RDL. i can remove all layers except single layer (capacitor layer) i found it AL_RDL if you use cadence you will find in via >>stack >>from metal A to metal B choose metal A...
  6. Z

    MIMCAP_130MML130n connection

    I found the layer AL_RDL which is found between two metal layer thanks for your consideration
  7. Z

    [SOLVED] ERROR_during running LVS

    hi i am using MOMCap in UMC130nm technology i get this error while running LVS i cant understand what is it mean ? thanks
  8. Z

    MIMCAP_130MML130n connection

    Hi i hope you are doing well I am using MIMCap_MML130E in umc130nm technology for first time and i don't now how to connect the terminal and what layers should i use what vias ? I attached below a multiplier Thanks in advance
  9. Z

    error during running calibare pex simulations

    can i know what is the extension of PEX file i have got calview .cellmap
  10. Z

    error during running calibare pex simulations

    i am using umc130nm technology i get this massage during running PEX simulation after passing DRC and LVS what sholud i do ?? finally anyone use ahdllib switch it has 2 parameter Vth and model what is the meaning by this ? Thanks for all interest
  11. Z

    sizing Transmission Gate to get suitable speed

    Hi how can i do sizing of Transmission gate to get suitable speed in my DAC i used binary wighted current steering
  12. Z

    error in printing parasitics in cadence virtuoso

    Re: error in printing parasitices in cadence virtuoso ahaa oky i don't know that i am just doing schematic till now . Thanks
  13. Z

    error in printing parasitics in cadence virtuoso

    Hi i am running transient analysis plus DC analysis and i want to know parasitics i choose print show parasitics i get this error *Error* hdbGetLibName: argument #1 should be a hierarchical database configuration object (type template = "h") - nil whats the problem >> thanks
  14. Z

    transient analysis in cadence virtuoso

    Dear all, i am design neural stimulator and i have connection between source and gate of transistor what is the impact of this connection? can i use DC source in transient analysis ? the input signals raising ramp and falling and rect thanks in advance
  15. Z

    [Moved]: GM-Cell VS Op-AmP

    i have question related to Gm-cell difference and op -Amp why we use Gm-cell in high frequency applications whats the benefits from op-amp and Gm-cell when i choose this style or this style (some else other frequency constrain ) if any one have reference in Gm-cell advice me please...
See more

Part and Inventory Search

Back
Top