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I think dividing analog block vdd/gnd and guard ring vdd/gnd is prefered way. if possible, they must connect to different vdd/gnd pad; if no more pad space left, you'd better route different power line, and connect them on pad side.
I have a HSPICE U model (cell u1wire in analoglib), but spectre do not surpport U model, how to do with it? whether I can use HspiceS instead of spectre?
Thanks
Re: PLL Design
I dont think you can calculate jitter using simulation. You can only estimate using models (Hajimiri or Razavi) by introducing major noise source (VCO noise & supply noise). And it is not easy to get 50ps c-2-c jitter using CMOS ring oscillator.
dear all,
My problem is:
How to satisfy the driving strength and output impedence requirement of Push-Pull PAD?
Anougth question: there is some solution to do slew rate control, what is preferred?
thanks
Re: do people include bandgap current reference in PLL desig
PLL has analog part and digital part, just put bandgap away from digital part, that's enough
for 3-order & 4-order charge pump pll, you can refer to "A cmos frequency synthesizer with an injection-locked frequency divider for a 5ghz wireless lan receiver" jssc may. 2000, for how to decide the loop filter parameters. And about you design, I have a question that why the reference...
you DO not need connect the gate of M1&M3 to node X, just get rid of it and connected to the output of OP. And what about the gate of M2&M4 ? just refer to Razavi's book to find out how to bias the cascode stage.
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