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Re: how to fix setup time violation after synthesis, don't lower the operating freque
many ways to fix setup violation after synthesis.
1. size cell and minimize data path delay.
2. check hold margin and useful skew.
3. use LVT cell
if all ways can not work. you 'd better add more margin to...
Re: Timing is clean yet data tran violation is there
No. You'd better fix clock MTTV and Data MTTV first.
If there are big transition exist, delay calculation will not accurate, so you said "timing is clean" is a "false path"
I think you'd better fix R2R setup timing , then fix all hold timing for R2R , IO path.
Finally, you'd better clear all hold, if setup spec can not meet, you can slow down the clock frequency to meet.
Every company has their own deisgn flow and design margin according their libarary.
So. If you want to do synthesis or pre-layout STA, you must follow that margin guider, for example, ZWLM, 55% clock cycle as shrink ratio.
And for input/output delay, you can make it tighten enough in order to...
ncsim linedebug
"X" means your netlist simulation surely have some setup/hold timing violation. you 'd better get the waveform and debug which is the source of X generation
Is there any good book or document focus on SoC archi design and analyse ?
I need it....
or somebody give me some advices about how we start a SoC architecture deisgn. and which aspect we should take a deep consideration...
thanks
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