Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
It is crazy! So I have the sampling frequency and then dividing by the number of channels I can set the stop frequency. For what concerns the cut-off...it is simply free! Crazy...provocatively I would select a 2nd or 3rd order filter :)
Hy guys,
I have to design an anti-aliasing filter for a 16-bit ADC with a sampling frequency of 200 kHz with the following specification:
- Pass Band Gain H=10dB with +/- 1 dB ripple
- Off Band Gain Hoff=-40dB
My understanding is that the staff frequency (the one at -40dB) should be 200kHz/2...
Yes, basically my question is if my understanding of the problem is correct and if it is possible to realize something better than what I have already designed.
Thanks
Thanks for your answers, i fully agree, the specification is not hazy. I report here the full text of the exercise:
- To Design a First Order Notch filter as in figure, using the minimum number of Op-Amp.
Hi guys,
I have an exercise which ask to design a suitable 1st order pass-band active filter in order to satisfy the attached specification. My understanding of the exercise is the following:
- I have to use two 1st order filter in cascade (LP+HP filter) in order to have the 20dc/decade slope...
Hy guys,
I have a simple non-inverting amplifier and I need to plot, with LTSpice, the I/O characteristic (Vout/Vin). Do you know how I can obtain this output by using LTSpice?
Thanks!
Thanks for your answer! So, you are proposing to replace both frequency divider and frequency selector by the megafunction Clock Control Block (ALTCLKCTRL), right? In this case my project will be simply a Clock Control Block+counter.
I will try it and I will let you now.
Thanks!
Hi guys,
I should design a 4 bit UP/DOWN digital counter with 1/10/100 kHz programmable clock frequency. I have to deal with an internal clock frequency around 50 MHz imposed by the cristal oscillator.
Unfortunately I have to use the Quartus Prime environment and I have some problem in finding...
Hi Guys,
I hope that this section is the right one. I think that there are also some thread relevant to control system design.
In details, I have a feedback contro system as follow:
r---->O---->Gc----->Gp----->O---->y
|...
Hi guys,
I have a common (I think) question related to the design of a schmitt trigger by using op-amp. In details I have to design a trigger with thresholds equal to +/- 1 V.
In order to do that, from the equation I have obtained that the ratio between the two resistance should by 14. Then I...
Thank you very much for the help!
I have a last question: are the transimpedance and the inverting amplifier connected to the R-2R ladder network necessary in this circuit? I saw a circuit in which the output of the R-2R was directly connected to the comparator.
Thanks!
Thanks guys for your answers. The circuit was just an idea and so didn't include resistor values but you are right, it is better to speak looking at the complete circuit below. I attach also the asc file.
**broken link removed**
Thank you very much for your help!
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
