Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
cadence sta tool
For DFT, Cadence has Encounter Test which can provide Test synthesis, Test Generation and Diagnostic.
You can also use RTL Compiler to do the test synthesis.
Re: clock jitter?
There are three types of clock jitter: first one is :long-term jitter, the 2nd is : period jitter, the 3rd one is : cycle-to-cycle jitter. all of these three type of jitter are presentation of clcok phase noise. Just like "Distance","Speed",and"Velocity"!
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
