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I think estimation means it is not quite correct.
and this data is only for other team's reference.
RAM die size can be getten from RAM specification and congestion factor is not consided.
Gate count is caculated with 2-nand area and synthesis area addition congestion (from other projects...
fifo?
You can search "FIFO design" by google, There are many pervious topics and many materials about FIFO are provided. SNUG has some excellent papers for this.
smart queue in vera
I don't think it's a methodology question.
The first case, memory space is required to store the data. but for second, not needed.
For verification protocol, these two are ok.
IP cores company
Yes, I think IP cores is a big opportunity for new company. Now the biggest companies dominate the IC market, but these companies lack innovation. and they will purchase many IPs for other IP cores company. but in other side, there are many IP design companies in the world...
It should be dealed with two different cases.
1. Real violation, debug and find the reason to cause x and solve it.
2. No a function issue and only the simualtion cause it. --- disable it to transfer to next stage. there is a xfilter parameter register in some library, you can set xfilter = 1 to...
Gate level simulation: check the function on netlist with timing information.
System validatin: Maybe the post silicon test. check the function on real chip.
Re: Please shed some light on "Post Silicon Validation&
Like the chip level simulation, should understand spec well.
To check the function and performance for your chip.
The early stage, only run the tests for all the modules without OS.
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