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Hi!
I received multiple SDF files for the same module. The sdf files are for
-functional mode
-shift mode during dft
-capture mode during dft
-mbist and bsd
Each of those sdf above contains min,typ,max, as usual. My question, during simulation,
-do I read all those sdf, or i just need to read...
Hi all..
Currently I'm doing verification for rtl versus netlist.
The netlist haven't been modified. It comes right after
being sythesized by Synopsys Design Compiler.
The main question in my mind is, why I need to verify the netlist. Is it
means that the tools cannot be trusted? In other...
Check the timeout limit. Since you said, after 10 hours, it stopped, that means, your timeout limit is 10 hours. You can set it to any number of minutes/hours or even unlimited.
I can't remember what's the command. Check the solvnet or manual.
Re: Latch synthesis
Will this code is synthesized into latch?
always @ (posedge clk)
begin
if (!rst)
out <= 0;
else
begin
if (enable)
out <= din;
end
end
In the above code, only if statement exist, but no else. But there a
reset condition. So, will this...
what do you mean by read spare cell in DC?
The only command that I know is "insert_spare_cells",
but that command is not recognized by dc, eventhough
that command is shown if I type dc_shell-t>man insert_spare_cells.
What other command should I use in DC, or does it not working
in DC (back to...
Actually, I was asked by layout person to do this.
This is the first time I heard about spare cells. So, I'm
still learning. And so far, I only use DC, not physical compiler.
I check the manual, the command does exist in physical compiler,
which is psyn_shell-t> insert_spare_cells -lib_cell...
insert_spare_cells
I have two questions regarding above.
1) Can I insert spare cells using Synopsys design compiler?
2) What are things that need to be considered if I want to do
compilation for design that have spare cells. What I mean
is do I have to do set dont touch for the...
I like the solution gave by Raptor. I tried it, and it works.
To me, this is the simplest one. Thank you.
But I hope someone can help me find the articles in solvnet.
I'm also still trying to find it.
synopsys netlist + solvnet
How do I remove assign statement in a synthesized netlist?
I read somewhere on the net, this assign statement exists
because
1) Input connected directly to output port
2) There is tristate cell
I'm more concern on how to solve the (1) because in my design,
there...
verilog $fwrite
I don't get your question. Do you mean to use it in a "for loop"?
Even for loop, you may need to write it in an initial block.
initial
begin
for (i=0;i<5;i=i+1)
$fwrite(osi, "aaa");
end
Or, you can use it in always block, something like this
always @ (posedge clk)...
Re: what is difference of SRAM and Synchronous Rigster File
So, when someone says, data buffer, does it means,
it could be either register(DFF) or RAM?
In verilog coding, does it have different coding style
to refer to data buffer using registers and to refer to RAM?
In verilog, if I declare...
Re: setup and holdtime
Try to take VLSI course, where you'll have to study
the internal structure of flip flop, delays, resistance,
and capacitance, and do the layout. You'll get a clear
picture. Or, just read a VLSI book.
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