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Thanks for your reply. I don't exactly know if I have access to PrimeTime or not in my server system which I use. What is the command to run PrimeTime?
Dear All,
I need to extract the power consumption trace of my circuit in Design Compiler using a VCD file. I know that I can extract an estimation of power consumption using the Saif file. However, this provides me with a single scalar value. What I need is a power trace over time and not just...
Dear all,
I need to feed a sample circuit with a number of random inputs (say for example 1000 input patterns) and then obtain a power trace (power consumed by the circuit during applying the input patterns). As the test circuit may not be small or the number of input patterns may be high, i...
Dear all,
I have a synthesized gate-level netlist and need to provide it with multiple input test pattern and extract the total power consumption of the whole circuit during the circuit operation (I want to plot the power consumption of the circuit while its input test patterns are changed). Is...
Yes. I need a plot which represents the trend of power consumption change over time. What I exactly need is the values of power consumption at different moments of time while the input vector is randomly changing.
Hi all,
I want to obtain a power trace from a circuit in Hspice. I don't know how to do this. To be more specific about my problem, assume a circuit with a simple 2-input AND gate. While one input (say, input A) is fixed at logic 1, the other input (input B) oscillates between 0 and 1, and hence...
Hi,
When i import a design into SDK (ISE design suite 14.7) and create a board support package, i get the error below:
Staging source files.
Running DRCs.
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"...
Hi all,
I want to use nangate 45nm technology for my spice simulations. When i use the spice models provided in this technology i get the following error:
unfound the model definition: pmos_vtl
All MOSFET transistors defined in spice models are of nmos_vtl/pmos_vtl models. Where are these...
Dear all,
How can i import cell delay from an SDF file into Hspice? For a specific project, i should create layout for my designs to obtain accurate delay models. I use SOC Encounter to create the layouts and obtain cell delays using
generated SDF file. Now, i want to model my circuits with...
Hi all,
I need to know how much post-layout simulation is accurate. I need some data and measurement results that compare real chip measurement with post-layout simulation results. I searched deeply through the internet but all i found was some qualitative data instead of quantitative data. All...
Hello everyone,
I want to know some materials about implementing capacitors in advanced VLSI circuits (below 100nm). First of all, which methods are used to implement capacitors? Based on what i found, currently, MOS capacitors, MIM (Metal-Insulator-Metal) and MOM (Metal-Oxide-Metal) are...
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