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Hi all,
I am implementing the IEEE paper.I want to measure the output current in Cadence Virtuoso tool.
The circuit to be implemented is as shown below.This is a Current mode Winner Take All circuit. The inputs are current .I have inserted the current source as shown in the red colour circles...
I think the better way to know the min/max values of W and L ...Put some extraordinarily low and high value to get the the range as said by Braski.
Further DK means Process Design Kit supplied to you by foundry else it is called GPDK if supplied by Cadence.
Hi all,
I am implementing a IEEE paper for ADC using inverters. I uses weghted inverters for 0.3um tech process.
The inverters are as weighted 15,8,4,2,1 .
does this means W/L ratios ?
Hi ,
I am want to know how to determine the W/L ratios for the particular transistor needed.I am implementing a IEEE paper in 350nm tech process log domain filter(3.3V) .
But i am using 180nm technology(min L=180nm and W=2um)..so i tried to maintain all the aspect ratios and scaled down to fit...
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