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Hello all. Can someone explain to me how the SRAM cell manages to retain its data when you implement power-gating? Assuming a 6T cell architecture, once you assert sleep, the back to back inverters will have lost power..how does it retain it's value?
thanks in advance.
New to the forum, so this may be in the wrong section, my pre-emptive apologies to anyone who may care.
Can someone explain to me why one would prefer one over the other (NMOS vs PMOS) sleeper when power-gating? My initial sentiment is that it depends on the output of the circuit, is this...
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