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Hi, I'm using the same technology as u did. I got the DRC error: (GR131_ana violation)
((Gates not over TG) NOT covered by GRLOGIC) OR ((Gates not over TG) under QT MIM capacitor) must have a RX tiedown by M1 metal.
I tried to tiedown for PMOS in nwell by placing a cell(ptiedown) from the 7rf...
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