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Hi, guys
We are designing an ASIC chip based on TSMC 40 technology. The nominal voltage is 1.1v (VDD) and the maximum clock frequency is 500MHz. We define static IR drop criteria as no more than VDD*5% (including VDD and VSS) and dynamic IR drop criteria as no more than VDD*15% (including VDD...
My team is designing a algorithm IP which need high throughput continuous data transaction, say, 64bits@800MHz or even higher. We plan to implement a DMA controller in this IP and use it to connect to DDR to perform high data-rate read/write transaction. What I want to know is should I use AHB...
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