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Recent content by yuxiaojian01

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    [SOLVED] [Moved] IBM 130nm Calibre PEX error

    Hi Erikl, Thank you for your reply. I put this label on the substrate contact, but it still can't work. Then some other guy in our department told me it may caused by the calibre cellmap file. He gave me a new cellmap file which does not include devicepad symbol, and the PEX passed.
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    [SOLVED] [Moved] IBM 130nm Calibre PEX error

    Hi everyone, I am using IBM 130nm cmrf8sf PDK. I made a simple inverter and performed DRC, LVS, PEX with Calibre. The DRC and LVS work well, but there is a PEX error shown as follows: "error: Could not find pin mapping for terminal sub of cell (cmrf8sf devicepad symbol). It will remain...
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    Anyone knows what kind of transistor is it?

    Thank you erikl, that solves the question.
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    Anyone knows what kind of transistor is it?

    Thank you for your reply. I got it from a paper, it's in the attachment. I think it's a HV Mosfet, but I'm not sure.
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    Anyone knows what kind of transistor is it?

    Hi all, do you know what is the name of this transistor? It should be a NMOS transistor, but why is there a small rectangular of the symbol? What is the meaning of it? what is the difference between it and the normal NMOS transistor? Thank you!
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    cadence layout warning: gate used as conductor

    Thank you, Erikl!
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    cadence layout warning: gate used as conductor

    Hi,everyone, There is a warning "gate used as conductor" after DRC when I use cadence to create layout. The layout is shown in the figure. What's the meaning of the warning? Does that mean I can't connect two transistor's gate using poly? Thanks.
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