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Hi Davison,
There could be multiple reasons for it. First of all let us know if this is CTDSM or DTDSM. Second what's ur DC gain & UGB of ur First int? Do you use Dithering or something else for DAC? or this could be because of some dynamic error too. Give us more insight into ur design so as...
Yes, I agree with LuW. You cannot actually split the operation into linear and non-linear one. And if you are checking your harmonic behavior of your open loop amplifier then I would prefer both the analysis to be carried out. (and the FFT analysis is a must for these open loop amplifier choose...
Kenambo,
First are you checking an comparator or opamp. If opamp, I wonder why you would want to check it in open loop. And if you are checking for a small signal operation, considering the second stage is NMOS CS (for eg), then the gate voltage of NMOS CS cannot change lineraily, since the...
There are many self biased bandgap voltage, which biases it's own tail current but will require very carefully designed start up circuitary. Or you can generate current from constant gm(PTAT) bias circuits which don't need any reference currents.
Hi FvM,
I assume when we break the loop at the output of the opamp, then too we are defining the DC bias points by both the loops (Let say breaking the loop the traditional way). And also for eg, lets take const gm circuit with resistor degeneration on NMOS side. Then LG by breaking NMOS...
see, there is no global transient time defined, rather it's defined by the load circutary which gets connected. So, get the specification for that. And yes, seeing you simulation results it seems load regulation is slow. And as I have mentioned previously, you cannot expect the load regulation...
No. As long as you break the loop in a way that doesn't have any other inherent minor loop inside it, the loop analysis will give you proper results. If you are breaking the loop at the opamp output, then you are injecting equal test signal to both the loop, so that should give you proper results.
I assume you're -ve resistance is done by some common source stage...So, you can refer Vittoz (I forgot ) for optimial sizing of the gm stage..and thus the current required.
This is a general problem in Capless Arch. You cannot vouch for fast load change. I guess there would be a spec for the load current profile. ACtually the arch you have chosen is generally used for De-cap LDO's. For the capless one, you need an additional fast loop which controls the gate of...
Hi, just try giving slow (relatievely) changing load of 0-->50mA. check if the oscillations are still there. Large signal oscillations are generally due to the slew. As you have mentioned if the slew makes the system slower then it's typically looks like a higher order system and thus instability.
What do you mean by de-Q'd? How much is the Q in the Xtal model. Low Q are always faster but will give slightly different Center frequencies. Generally in my simulation I assume Q of abt 50K. But this frequency shift doesnt matter unless u are trying to do some jitter sims.
Hi,
First thing is not to connect a ideal current source load. I suppose your LDO is not able to supply the current requested by the current source and hence tries to take the output voltage to -20v. How much is your Cp? Is the stability proper under DC load conditions of 50mA?
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