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Recent content by Yuphone

  1. Yuphone

    i2c to i2c switch in FPGA

    Wow, Brother UP had been here.
  2. Yuphone

    How to generate a pattern for generating divide by 5 clk ?

    Re: divide by 5 clock module div_by_5 ( input i_clk, input rst_n, output o_clk ); parameter N = 5; reg [3:0] cnt_p; reg [3:0] cnt_n; reg clk_p; reg clk_n; assign o_clk = clk_n & clk_p; always @ (posedge i_clk or negedge rst_n) begin if (!rst_n) cnt_p <= 0; else...
  3. Yuphone

    Algorithm used for a divider (Verilog)

    Divider well, there is a blog article about divider. https://www.cnblogs.com/oomusou/archive/2008/07/16/verilog_clock_divider.html It's in Chinese, but you can use Google Language Tools to translate it into English. In addtion, it's very detailed in both explanation and Verilog HDL description.
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